74ABT573(1999) データシートの表示（PDF） - Fairchild Semiconductor
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74ABT573 Datasheet PDF : 11 Pages
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Functional Description
The ABT573 contains eight D-type latches with 3-STATE
output buffers. When the Latch Enable (LE) input is HIGH,
data on the Dn inputs enters the latches. In this condition
the latches are transparent, i.e., a latch output will change
state each time its D input changes. When LE is LOW the
latches store the information that was present on the D
inputs a setup time preceding the HIGH-to-LOW transition
of LE. The 3-STATE buffers are controlled by the Output
Enable (OE) input. When OE is LOW, the buffers are in the
bi-state mode. When OE is HIGH the buffers are in the high
impedance mode but this does not interfere with entering
new data into the latches.
Logic Diagram
Function Table
Inputs
OE
LE
D
L
H
H
L
H
L
L
L
X
H
X
X
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
O0 = Value stored from previous clock cycle
Outputs
O
H
L
O0
Z
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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