MC74HC4020AD データシートの表示（PDF） - Motorola => Freescale
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MC74HC4020AD Datasheet PDF : 8 Pages
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
14-Stage Binary Ripple
Counter
High–Performance Silicon–Gate CMOS
The MC74C4020A is identical in pinout to the standard CMOS
MC14020B. The device inputs are compatible with standard CMOS outputs;
with pullup resistors, they are compatible with LSTTL outputs.
This device consists of 14 master–slave flip–flops with 12 stages brought
out to pins. The output of each flip–flop feeds the next and the frequency at
each output is half of that of the preceding one. Reset is asynchronous and
active–high.
State changes of the Q outputs do not occur simultaneously because of
internal ripple delays. Therefore, decoded output signals are subject to
decoding spikes and may have to be gated with the Clock of the HC4020A
for some designs.
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance With JEDEC Standard No. 7A Requirements
• Chip Complexity: 398 FETs or 99.5 Equivalent Gates
LOGIC DIAGRAM
Clock 10
9 Q1
7 Q4
5 Q5
4 Q6
6 Q7
13 Q8
12 Q9
14 Q10
15 Q11
1 Q12
2 Q13
3 Q14
Reset 11
Pin 16 = VCC
Pin 8 = GND
VCC Q11 Q10 Q8 Q9 Reset Clock Q1
16 15 14 13 12 11 10 9
Pinout: 16–Lead Plastic Package
(Top View)
12345678
Q12 Q13 Q14 Q6 Q5 Q7 Q4 GND
MC74HC4020A
16
1
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
16
1
D SUFFIX
SOIC PACKAGE
CASE 751B–05
16
1
DT SUFFIX
TSSOP PACKAGE
CASE 948F–01
ORDERING INFORMATION
MC74HCXXXXAN
MC74HCXXXXAD
MC74HCXXXXADT
Plastic
SOIC
TSSOP
Clock
X
FUNCTION TABLE
Reset
L
L
H
Output State
No Charge
Advance to Next State
All Outputs Are Low
10/95
© Motorola, Inc. 1995
3–1
REV 1
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