WME128K8 データシートの表示（PDF） - Microsemi Corporation
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WME128K8 Datasheet PDF : 12 Pages
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WME128K8-XXX
READ
Figure 3 shows Read cycle waveforms. A read cycle begins with
selection address, chip select and output enable. Chip select is
accomplished by placing the CS# line low. Output enable is done
by placing the OE# line low. The memory places the selected data
byte on I/O0 through I/O7 after the access time. The output of the
memory is placed in a high impedance state shortly after either
the OE# line or CS# line is returned to a high level.
FIGURE 3 – READ WAVEFORMS
ADDRESS
t RC
ADDRESS VALID
CS#
OE#
t ACS
t OE
t ACC
OUTPUT
HIGH Z
NOTE:
OE# may be delayed up to tACS- tOE after the falling edge of CS#
without impact on tOE or by tACC- tOE after an address change without impact on tACC.
t DF
t OH
OUTPUT
VALID
AC READ CHARACTERISTICS (See Figure 3)
VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C
Read Cycle Parameter
-125
-140
-150
-200
-250
-300
Symbol
Unit
Min Max Min Max Min Max Min Max Min Max Min Max
Read Cycle Time
tRC
125
140
150
200
250
300
ns
Address Access Time
tACC
125
140
150
200
250
300
ns
Chip Select Access Time
tACS
125
140
150
200
250
300
ns
Output Hold from Address Change, OE#
or CS#
tOH
0
0
0
0
0
0
ns
Output Enable to Output Valid
tOE
55
55
55
55
85
85
ns
Chip Select or OE# to High Z Output
tDF
63
70
70
70
70
70
ns
Microsemi Corporation reserves the right to change products or specifications without notice.
July 2011 © 2011 Microsemi Corporation. All rights reserved.
3
Rev. 7
Microsemi Corporation • (602) 437-1520 • www.microsemi.com
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