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CXA2066S データシートの表示(PDF) - Sony Semiconductor

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CXA2066S Datasheet PDF : 21 Pages
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CXA2066S
I2C BUS Register Definitions
Slave Address
SLAVE RECEIVER; 40 (HEX)
Register Table
SUB ADDRESS
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
BIT7
BIT6
0
BLK
MODE
VDET LEVEL
V DET
OFF
SHP
OFF
BIT5
BIT4
BIT3
CONTRAST
BIT2
BIT1
BRIGHTNESS
SYNC
OFF
CUT OFF R
CUT OFF G
CUT OFF B
OSD GAIN
CUT OFF RGB
SUB CONTRAST R
SUB CONTRAST G
SUB CONTRAST B
T SW
SHP GAIN
BIT0
Sub Address CONTRAST (8)
0000
Controls the gain common to the R, G, and B channels. Since control is
performed by multiplying with SUB CONTRAST, the white balance can
be adjusted by SUB CONTRAST and the luminance can be adjusted by
CONTRAST.
0: Gain minimum (–30dB or less)
255: Gain maximum (+17dB)
Sub Address BLK MODE (1)
0001
Switches the blanking level.
0: Pedestal –0.6V
1: 0.5V fixed
Sub Address BRIGHTNESS (6)
0001
Controls the black level common for the R, G, and B channels.
0: Black level minimum (1V)
63: Black level maximum (3V)
Sub Address CUT OFF R (8)
0010
Controls Pin 3 (COF R) output voltage.
0: Output voltage minimum (1V)
255: Output voltage maximum (4V)
Sub Address CUT OFF G (8)
0011
Controls Pin 4 (COF G) output voltage.
0: Output voltage minimum (1V)
255: Output voltage maximum (4V)
Sub Address CUT OFF B (8)
0100
Controls Pin 5 (COF B) output voltage.
0: Output voltage minimum (1V)
255: Output voltage maximum (4V)
–7–

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