AD7476ARTZ-500RL7 データシートの表示（PDF） - Analog Devices
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AD7476ARTZ-500RL7 Datasheet PDF : 24 Pages
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AD7476/AD7477/AD7478
AD7478 SPECIFICATIONS
VDD = 2.7 V to 5.25 V, fSCLK = 20 MHz, TA = TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
DYNAMIC PERFORMANCE
A Version1,2 S Version1,2 Unit
Signal-to-(Noise + Distortion) (SINAD)3
49
49
dB min
Total Harmonic Distortion (THD)3
−65
−65
dB max
Peak Harmonic or Spurious Noise (SFDR)3
−65
−65
dB max
Intermodulation Distortion (IMD)3
Second-Order Terms
−68
−68
dB typ
Third-Order Terms
−68
−68
dB typ
Aperture Delay
10
10
ns typ
Aperture Jitter
30
30
ps typ
Full Power Bandwidth
6.5
6.5
MHz typ
DC ACCURACY
Resolution
Integral Nonlinearity3
Differential Nonlinearity3
Offset Error
Gain Error
Total Unadjusted Error (TUE)
ANALOG INPUT
8
8
Bits
±0.5
±0.5
LSB max
±0.5
±0.5
LSB max
±0.5
±0.5
LSB max
±0.5
±0.5
LSB max
±0.5
±0.5
LSB max
Input Voltage Ranges
DC Leakage Current
Input Capacitance
LOGIC INPUTS
0 to VDD
±1
30
0 to VDD
±1
30
V
μA max
pF typ
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN, SCLK Pin
Input Current, IIN, CS Pin
Input Capacitance, CIN4
LOGIC OUTPUTS
2.4
2.4
V min
0.8
0.8
V max
0.4
0.4
V max
±1
±1
μA max
±1
±1
μA typ
10
10
pF max
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance4
Output Coding
CONVERSION RATE
VDD − 0.2
VDD − 0.2
0.4
0.4
±10
±10
10
10
Straight (Natural) Binary
V min
V max
μA max
pF max
Conversion Time
Track-and-Hold Acquisition Time
Throughput Rate
POWER REQUIREMENTS
800
800
ns max
400
400
ns max
1
1
MSPS max
VDD
IDD
Normal Mode (Static)
Normal Mode (Operational)
Full Power-Down Mode
2.7/5.25
2
1
3.5
1.6
1
80
2.7/5.25
2
1
3.5
1.6
1
80
V min/max
mA typ
mA typ
mA max
mA max
μA max
μA max
Test Conditions/Comments
fIN = 100 kHz sine wave, fSAMPLE = 1 MSPS
fa = 498.7 kHz, fb = 508.7 kHz
fa = 498.7 kHz, fb = 508.7 kHz
@ 3 dB
Guaranteed no missed codes to eight bits
VDD = 5 V
VDD = 3 V
Typically 10 nA, VIN = 0 V or VDD
ISOURCE = 200 μA, VDD = 2.7 V to 5.25 V
ISINK = 200 μA
16 SCLK cycles with SCLK at 20 MHz
See Serial Interface section
Digital I/Ps = 0 V or VDD
VDD = 4.75 V to 5.25 V, SCLK on or off
VDD = 2.7 V to 3.6 V, SCLK on or off
VDD = 4.75 V to 5.25 V, fSAMPLE = 1 MSPS
VDD = 2.7 V to 3.6 V, fSAMPLE = 1 MSPS
SCLK off
SCLK on
Rev. F | Page 7 of 24
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