AD7476ARTZ-500RL7 データシートの表示（PDF） - Analog Devices
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AD7476ARTZ-500RL7 Datasheet PDF : 24 Pages
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AD7476/AD7477/AD7478
Parameter
Power Dissipation5
Normal Mode (Operational)
Full Power-Down
A Version1,2 S Version1,2 Unit
17.5
17.5
mW max
4.8
4.8
mW max
5
5
μW max
1 Temperature range for A version is −40°C to +85°C; temperature range for S version is −55°C to +125°C.
2 Operational from VDD = 2.0 V, with input high voltage, VINH = 1.8 V minimum.
3 See the Terminology section.
4 Guaranteed by characterization.
5 See the Power vs. Throughput Rate section.
Test Conditions/Comments
VDD = 5 V, fSAMPLE = 1 MSPS
VDD = 3 V, fSAMPLE = 1 MSPS
VDD = 5 V, SCLK off
TIMING SPECIFICATIONS
VDD = 2.35 V to 5.25 V, TA = TMIN to TMAX, unless otherwise noted.
Table 4.
Parameter 2 , 3
fSCLK 4
Limit at TMIN, TMAX1
3V
5V
10
10
20
20
12
12
tCONVERT
tQUIET
t1
t2
t3 5
t45
t5
t6
t7
t8 6
tPOWER-UP 7
16 × tSCLK
50
10
10
20
40
70
0.4 ×
tSCLK
0.4 ×
tSCLK
10
10
25
1
16 × tSCLK
50
10
10
20
20
20
0.4 ×
tSCLK
0.4 ×
tSCLK
10
10
25
1
Unit
kHz min
MHz
max
MHz
max
ns min
ns min
ns min
ns max
ns max
ns max
ns min
ns min
ns min
ns min
ns max
μs typ
Description
A version
B version
Minimum quiet time required between bus relinquish and start of next conversion
Minimum CS pulsewidth
CS to SCLK setup time
Delay from CS until SDATA three-state disabled
Data access time after SCLK falling edge, A version
Data access time after SCLK falling edge, B version
SCLK low pulsewidth
SCLK high pulsewidth
SCLK to data valid hold time
SCLK falling edge to SDATA high impedance
SCLK falling edge to SDATA high impedance
Power-up time from full power-down
1 3 V specifications apply from VDD = 2.7 V to 3.6 V for A version; 3 V specifications apply from VDD = 2.35 V to 3.6 V for B version; 5 V specifications apply from
VDD = 4.75 V to 5.25 V.
2 Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
3 Version A timing specifications apply to the AD7477 and AD7478 S version; B version timing specifications apply to the AD7476 S version.
4 Mark/space ratio for the SCLK input is 40/60 to 60/40.
5 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V.
6 t8 is derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit in Figure 2. The measured number is then extrapolated to
remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, is the true bus relinquish time of the part and is independent of the bus
loading.
7 See Power-Up Time section.
200µA
IOL
TO OUTPUT
PIN CL
50pF
1.6V
200µA
IOH
Figure 2. Load Circuit for Digital Output Timing Specifications
Rev. F | Page 8 of 24
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