AD5425 データシートの表示（PDF） - Analog Devices
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AD5425 Datasheet PDF : 24 Pages
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Data Sheet
AD5425
TIMING CHARACTERISTICS
All input signals are specified with tr = tf = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. VDD =2.5 V to 5.5 V,
VREF = 10 V, IOUT2 = 0 V, temperature range for Y version: −40°C to +125°C ; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter1
fSCLK
t1
t2
t3
t4 2
t5
t6
t7
t8
t9
t10
t11
VDD = 2.5 V to 5.5 V
50
20
8
8
13
5
3
5
30
0
12
10
Unit
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Test Conditions/Comments
Maximum clock frequency
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
Data setup time
Data hold time
SYNC rising edge to SCLK falling edge
Minimum SYNC high time
SCLK falling edge to LDAC falling edge
LDAC pulse width
SCLK falling edge to LDAC rising edge
1 Guaranteed by design and characterization, not subject to production test.
2 Falling or rising edge as determined by control bits of serial word.
SCLK
SYNC
DIN
t8
t4
DB7
t6
t5
LDAC1
t1
t2
t3
t7
DB0
t10
t9
LDAC2
NOTES:
1ASYNCHRONOUS LDAC UPDATE MODE.
2SYNCHRONOUS LDAC UPDATE MODE.
t11
Figure 2. Timing Diagram
Rev. D | Page 5 of 24
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