AD7660(2016) データシートの表示（PDF） - Analog Devices

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AD7660
(Rev.:2016)

16-Bit, 100 kSPS PulSAR® Unipolar CMOS ADC

Analog Devices 

AD7660

CIRCUIT INFORMATION

The AD7660 is a fast, low power, single-supply, precise 16-bit

analog-to-digital converter (ADC). The AD7660 is capable of

converting 100,000 samples per second (100 kSPS) and allows

power saving between conversions. When operating at 100 SPS,

for example, it consumes typically only 21 mW. This feature

makes the AD7660 ideal for battery-powered applications.

The AD7660 provides the user with an on-chip track-and-

hold, successive-approximation ADC that does not exhibit any

pipeline or latency, making it ideal for multiple multiplexed

channel applications.

The AD7660 can be operated from a single 5 V supply and be

interfaced to either 5 V or 3 V digital logic. It is housed in a

48-lead LQFP package or a 48-lead LFCSP package that com-

bines space savings and allows flexible configurations as either

serial or parallel interface. The AD7660 is pin-to-pin compatible

with the AD7664.

CONVERTER OPERATION

The AD7660 is a successive-approximation analog-to-digital

converter based on a charge redistribution DAC. Figure 3 shows

the simplified schematic of the ADC. The capacitive DAC consists

of an array of 16 binary weighted capacitors and an additional

LSB capacitor. The comparator’s negative input is connected to

a “dummy” capacitor of the same value as the capacitive

DAC array.

During the acquisition phase, the common terminal of the array

tied to the comparator’s positive input is connected to AGND

via SWA. All independent switches are connected to the analog

input IN. Thus, the capacitor array is used as a sampling capaci-

tor and acquires the analog signal on IN input. Similarly, the

dummy capacitor acquires the analog signal on the INGND input.

When the acquisition phase is complete and the CNVST input

goes or is LOW, a conversion phase is initiated. When the con-

version phase begins, SWA and SWB are opened first. The

capacitor array and the dummy capacitor are then disconnected

from the inputs and connected to the REFGND input. There-

fore, the differential voltage between IN and INGND captured

at the end of the acquisition phase is applied to the comparator

inputs, causing the comparator to become unbalanced.

By switching each element of the capacitor array between REFGND

or REF, the comparator input varies by binary weighted voltage

steps (VREF/2, VREF/4 . . . VREF/65536). The control logic toggles

these switches, starting with the MSB first, in order to bring the

comparator back into a balanced condition. After the comple-

tion of this process, the control logic generates the ADC output

code and brings BUSY output LOW.

IN

REF

REFGND

MSB

LSB LSB SWA

SWITCHES

CONTROL

32768C 16384C

4C

2C

C

C

INGND

65536C

COMP

SWB

BUSY

CONTROL

LOGIC

OUTPUT

CODE

CNVST

Figure 3. ADC Simplified Schematic

–10–

REV. E

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