AR0141CS2C00SUEA0-DR(2015) データシートの表示（PDF） - ON Semiconductor
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AR0141CS2C00SUEA0-DR Datasheet PDF : 63 Pages
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AR0141CS: 1/4-Inch Digital Image Sensor
General Description
Figure 4: 9 x 9 mm 63-Ball IBGA Package
1
A
2
3
4
5
6
SLVS0_N SLVS0_P SLVS1_N SLVS1_P
VDD
7
8
VDD
STANDBY
B VDD_PLL SLVS_CN SLVSC_P SLVS2_N SLVS2_P
VDD
VAA
VAA
C EXTCLK
VDD_
SLVS
SLVS3_N SLVS3_P
DGND
VDD
AGND
AGND
D
SADDR
SCLK
SDATA
DGND
DGND
VDD
VAA_PIX
VAA_PIX
E
LINE_
VALID
FRAME_ PIXCLK
VALID
FLASH
DGND
VDD_IO
NC
NC
F
DOUT8
DOUT9
DOUT10
DOUT11
DGND
VDD_IO
TEST
Reserved
G
DOUT4
DOUT5
DOUT6
DOUT7
DGND
VDD_IO TRIGGER
OE_BAR
H
DOUT0
DOUT1
DOUT2
DOUT3
DGND
VDD_IO
VDD_IO
RESET_
BAR
Top View
(Ball Down)
Table 3:
Ball Descriptions, 9 x 9 mm, 63-ball iBGA
Name
SLVS0_N
SLVS0_P
SLVS1_N
SLVS1_P
STANDBY
VDD_PLL
SLVSC_N
SLVSC_P
SLVS2_N
SLVS2_P
VAA
EXTCLK
VDD_SLVS
SLVS3_N
SLVS3_P
iBGA Pin
A2
A3
A4
A5
A8
B1
B2
B3
B4
B5
B7, B8
C1
C2
C3
C4
Type
Output
Output
Output
Output
Input
Power
Output
Output
Output
Output
Power
Input
Power
Output
Output
Description
HiSPi serial data, lane 0, differential N.
HiSPi serial data, lane 0, differential P.
HiSPi serial data, lane 1, differential N.
HiSPi serial data, lane 1, differential P.
STANDBY (active high)
PLL power.
HiSPi serial DDR clock differential N.
HiSPi serial DDR clock differential P.
HiSPi serial data, lane 2, differential N.
HiSPi serial data, lane 2, differential P.
Analog power.
External input clock.
0.3V-0.6V or 1.7V - 1.9V port to HiSPi Output Driver. Set the High_VCM
(R0x306E[9]) bit to 1 when configuring VDD_SLVS to 1.7 – 1.9V.
HiSPi serial data, lane 3, differential N.
HiSPi serial data, lane 3, differential P.
AR0141CS DS Rev. D Pub. 6/15 EN
9
©Semiconductor Components Industries, LLC, 2015.
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