AR0141CS2C00SUEA0-DP データシートの表示（PDF） - ON Semiconductor

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AR0141CS2C00SUEA0-DP

1/4‐inch Digital Image Sensor

ON Semiconductor 

AR0141CS

Digital Digital

I/O Core

Power1 Power1

PLL Analog Analog

Power1 Power1 Power1

VDD_IO VDD

VDD_PLL VAA VAA_PIX

Master Clock

(6 − 50 MHz)

From Controller

EXTCLK

SADDR

SDATA

SCLK

TRIGGER

OE_BAR

RESET_BAR

TEST

DGND

DOUT [11:0]

PIXCLK

LINE_VALID

FRAME_VALID

FLASH

SHUTTER

AGND

VDD_IO

VDD

VDD_PLL

VAA

VAA_PIX

Digital

Ground

Analog

Ground

To Controller

Notes:

1. All power supplies must be adequately decoupled.

2. ON Semiconductor recommends a resistor value of 1.5 kW, but a greater value may be used for slower two−wire speed.

3. The serial interface output pads and VDD_SLVS can be left unconnected if the parallel output interface is used.

4. ON Semiconductor recommends that 0.1 mF and 10 mF decoupling capacitors for each power supply are mounted as

close as possible to the pad. Actual values and results may vary depending on layout and design considerations.

Check the AR0141CS demo headboard schematics for circuit recommendations.

5. ON Semiconductor recommends that analog power planes are placed in a manner such that coupling with the digital

power planes is minimized.

6. I/O signals voltage must be configured to match VDD_IO voltage to minimize any leakage current.

7. The EXTCLK input is limited to 6−50 MHz.

Figure 3. Typical Configuration: Parallel Pixel Data Interface

Table 3. BALL DESCRIPTIONS, 9 X 9 MM, 63−BALL iBGA

Name

iBGA Pin

Type

Description

SLVS0_N

A2

Output HiSPi serial data, lane 0, differential N

SLVS0_P

A3

Output HiSPi serial data, lane 0, differential P

SLVS1_N

A4

Output HiSPi serial data, lane 1, differential N

SLVS1_P

A5

Output HiSPi serial data, lane 1, differential P

STANDBY

A8

Input

Standby (active high)

VDD_PLL

SLVSC_N

B1

Power PLL power

B2

Output HiSPi serial DDR clock differential N

SLVSC_P

B3

Output HiSPi serial DDR clock differential P

SLVS2_N

B4

Output HiSPi serial data, lane 2, differential N

SLVS2_P

B5

Output HiSPi serial data, lane 2, differential P

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