ARM7TDMI データシートの表示（PDF） - Unspecified

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ARM7TDMI

General-Purpose 32-Bit Microprocessors

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Introduction

Fetch

Instruction fetched from memory

Decode

Execute

Decoding of registers used in

instruction

Register(s) read from register bank

Perform shift and ALU operations

Write register(s) back to register bank

Figure 1-1 Instruction pipeline

During normal operation, while one instruction is being executed, its successor is being

decoded, and a third instruction is being fetched from memory.

The program counter points to the instruction being fetched rather than to the instruction

being executed. This is important because it means that the Program Counter (PC)

value used in an executing instruction is always two instructions ahead of the address.

1.1.2

Memory access

The ARM7TDMI core has a Von Neumann architecture, with a single 32-bit data bus

carrying both instructions and data. Only load, store, and swap instructions can access

data from memory.

Data can be:

• 8-bit (bytes)

• 16-bit (halfwords)

• 32-bit (words).

Words must be aligned to 4-byte boundaries. Halfwords must be aligned to 2-byte

boundaries.

ARM DDI 0029G

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