KSZ9031RNX データシートの表示（PDF） - Micrel

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KSZ9031RNX

Gigabit Ethernet Transceiver with RGMII Support

Micrel 

Micrel, Inc.

KSZ9031RNX

Revision History

Revision

1.0

Date

10/31/12

2.0

07/31/13

2.1

11/18/14

2.2

5/14/15

Summary of Changes

Data sheet created

• Updated Functional Diagram with “PME_N” signal.

• Indicated pin type is not an open-drain for PME_N1 (Pin 17) and INT_N/PME_N2 (Pin 38).

• Deleted TSLP package height from Package Information(11) and Recommended Land Pattern.

• Added typical series resistance and load capacitance for crystal selection criteria.

• Added setup/hold timings for integrated delays per the RGMII v2.0 Specification.

• Added note that RGMII data-to-clock skews for 10/100Mbps speeds are looser than for 1000Mbps

speed.

• Corrected register definition for override strap-in for LED_MODE in MMD Address 2h, Register 0h.

• Clarified register description for software power-down bit (Register 0h, Bit [11]).

• Clarified power cycling specification to have all supply voltages to the KSZ9031RNX reach less

than 0.4V before the next power-up cycle.

• Added AEC-Q100 automotive qualified part numbers, KSZ9031RNXUA and KSZ9031RNXVA, to

General Description, Features, Ordering Information and Electrical Characteristics(10) sections.

• Added Package Information(11) and Recommended Land Pattern for 48-pin (7mm x 7mm)

WQFN for the automotive qualified part numbers.

• Corrected Package Information(11) and Recommended Land Pattern for 48-pin (7mm x 7mm)

QFN. This is a datasheet correction. There is no change to the 48-pin (7mm x 7mm) QFN package.

• Added note that internal pull-up values are measured with pin input voltage level at 1/2 DVDDH in

Electrical Characteristics(10) section.

• Corrected datasheet revision 2.1 formatting errors for Standard Register 13h.

• Added more details for XI (25MHz reference clock) input specification to Reference Clock –

Connection and Selection section.

• Added note in Standard Register 0h, Bit [12] to indicate when Auto-Negotiation is disabled, Auto

MDI-X is also automatically disabled.

• Added note in 10Base-T Receive section that all 7 bytes of preamble are removed.

• Added instruction in Register 9h, Bits [15:13] to enable 1000Base-T Test Mode.

• Added description in Auto-Negotiation Timing section to change FLP timing from 8ms to 16ms.

• Added MMD Address 0h, Registers 3h and 4h for FLP timing.

• Specified maximum frequency (minimum clock period) for MDC clock.

• Updated input leakage current for the digital input pins in Electrical Characteristics(10) section.

• Added minimum output currents for the digital output pins in Electrical Characteristics(10) section.

• Corrected output drive current for LED1 and LED2 pins in Electrical Characteristics(10) section.

• Updated Reset Circuit section and added reset circuit with MIC826 Voltage Supervisor.

• Clarified LED indication support for 1.8V DVDDH requires voltage level shifters.

• Added 10/100 Speeds Only section.

• Added section for MOSFET selection for optional on-chip LDO controller.

• Clarified RGMII timing and added Original RGMII (v1.3) timing with external delay for reference.

May 14, 2015

3

Revision 2.2

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