74VHC573 データシートの表示（PDF） - Fairchild Semiconductor

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74VHC573

Octal D-Type Latch with 3-STATE Outputs

Fairchild Semiconductor 

Functional Description

Truth Table

The VHC573 contains eight D-type latches with 3-STATE

output buffers. When the Latch Enable (LE) input is HIGH,

Inputs

data on the Dn inputs enters the latches. In this condition

OE

LE

D

the latches are transparent, i.e., a latch output will change

state each time its D input changes. When LE is LOW the

L

H

H

latches store the information that was present on the D

L

H

L

inputs, a setup time preceding the HIGH-to-LOW transition

of LE. The 3-STATE buffers are controlled by the Output

L

L

X

Enable (OE) input. When OE is LOW, the buffers are

H

enabled. When OE is HIGH the buffers are in the high

X

X

impedance mode, but, this does not interfere with entering H = HIGH Voltage Level

new data into the latches.

L = LOW Voltage Level

X = Immaterial

Z = High Impedance

Logic Diagram

Outputs

On

H

L

O0

Z

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

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