AD7545UE データシートの表示（PDF） - Analog Devices

部品番号

コンポーネント説明

メーカー

AD7545UE

CMOS 12-Bit Buffered Multiplying DAC

Analog Devices 

AD7545–SPECIFICATIONS (VREF = +10 V, VOUT1 = O V, AGND = DGND unless otherwise noted)

Parameter

STATIC PERFORMANCE

Resolution

Differential Nonlinearity

Gain Error (Using Internal RFB)2

Gain Temperature Coefficient3

∆Gain/∆Temperature

DC Supply Rejection3

∆Gain/∆VDD

Output Leakage Current at OUT1

Version

VDD = +5 V

Limits

TA = + 25؇C TMIN, TMAX1

VDD = +15 V

Limits

TA = + 25؇C TMIN, TMAX1

Units

Test Conditions/Comments

All

12

12

J, A, S

±2

±2

K, B, T

±1

±1

L, C, U

± 1/2

± 1/2

GL, GC, GU ± 1/2

± 1/2

J, A, S

±4

±4

K, B, T

±1

±1

L, C, U

±1

±1

GL, GC, GU ± 1

±1

J, A, S

± 20

± 20

K, B, T

± 10

± 10

L, C, U

±5

±6

GL, GC, GU ± 1

±2

All

±5

±5

All

0.015

0.03

J, K, L, GL 10

50

A, B, C, GC 10

50

S, T, U, GU 10

200

12

±2

±1

± 1/2

± 1/2

±4

±1

±1

±1

± 25

± 15

± 10

±6

± 10

0.01

10

10

10

12

±2

±1

± 1/2

± 1/2

±4

±1

±1

±1

± 25

± 15

± 10

±7

± 10

0.02

50

50

200

Bits

LSB max

LSB max

LSB max

LSB max

LSB max

LSB max

LSB max

LSB max

LSB max

LSB max

LSB max

LSB max

10-Bit Monotonic TMIN to TMAX

12-Bit Monotonic TMIN to TMAX

12-Bit Monotonic TMIN to TMAX

12-Bit Monotonic TMIN to TMAX

DAC Register Loaded with

1111 1111 1111

Gain Error Is Adjustable Using

the Circuits of Figures 4, 5, and 6

ppm/°C max Typical Value is 2 ppm/°C for VDD = +5 V

% per % max

nA max

nA max

nA max

∆VDD = ± 5%

DB0–DB11 = 0 V; WR, CS = 0 V

DYNAMIC PERFORMANCE

Current Settling Time3

All

Propagation Delay3 (from Digital

Input Change to 90%

of Final Analog Output)

All

Digital-to-Analog Glitch Inpulse

All

AC Feedthrough5

At OUT1

All

REFERENCE INPUT

Input Resistance

All

(Pin 19 to GND)

2

2

300

–

400

–

5

5

7

7

25

25

2

2

250

–

250

–

5

5

7

7

25

25

µs max

To 1/2 LSB. OUT1 Load = 100 Ω. DAC

Output Measured from Falling Edge of

WR, CS = 0.

ns max

nV sec typ

mV p-p typ

OUT1 Load = 100 Ω, CEXT = 13 pF4

VREF = AGND

VREF = ± 10 V, 10 kHz Sinewave

kΩ min

kΩ max

Input Resistance TC = –300 ppm/°C typ

Typical Input Resistance = 11 kΩ

ANALOG OUTPUT

Output Capacitance3

COUT1

COUT1

All

70

70

70

70

pF max

DB0–DB11 = 0 V, WR, CS = 0 V

200

200

200

200

pF max

DB0–DB11 = VDD, WR, CS = 0 V

DIGITAL INPUTS

Input High Voltage

VIH

Input Low Voltage

VIL

Input Current6

IIN

Input Capacitance3

DB0–DB11

WR, CS

All

2.4

2.4

13.5

13.5

V min

All

0.8

0.8

1.5

1.5

V max

All

±1

± 10

±1

± 10

µA max

VIN = 0 or VDD

All

5

5

5

5

pF max

VIN = 0

All

20

20

20

20

pF max

VIN = 0

SWITCHING CHARACTERISTICS7

Chip Select to Write Setup Time

All

tCS

Chip Select to Write Hold Time

tCH

All

Write Pulse Width

tWR

All

Data Setup Time

All

tDS

Data Hold Time

tDH

All

280

380

200

270

0

0

250

400

175

280

140

210

100

150

10

10

180

200

ns min

See Timing Diagram

120

150

ns typ

0

0

ns min

160

240

ns min

tCS ≥ tWR, tCH ≥ 0

100

170

ns typ

90

120

ns min

60

80

ns typ

10

10

ns min

POWER SUPPLY

IDD

All

2

2

2

2

mA max

All Digital Inputs VIL or VIH

100

500

100

500

µA max

All Digital Inputs 0 V to VDD

10

10

10

10

µA typ

All Digital Inputs 0 V to VDD

NOTES

1Temperature range as follows: J, K, L, GL versions, 0°C to +70°C; A, B, C, GC versions, –25°C to +85°C; S, T, U GU versions, –55°C to +125°C.

2This includes the effect of 5 ppm max gain TC.

3Guaranteed but not tested.

4DB0–DB11 = 0 V to VDD or VDD to 0 V.

5Feedthrough can be further reduced by connecting the metal lid on the ceramic package (Suffix D) to DGND.

6Logic inputs are MOS gates. Typical input current (+25°C) is less than 1 nA.

7Sample tested at +25°C to ensure compliance.

Specifications subject to change without notice.

–2–

REV. A

Share Link: