AD7545UE データシートの表示（PDF） - Analog Devices
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AD7545UE Datasheet PDF : 9 Pages
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AD7545
CIRCUIT INFORMATION—D/A CONVERTER SECTION
Figure 1 shows a simplified circuit of the D/A converter section
of the AD7545 and Figure 2 gives an approximate equivalent
circuit. Note that the ladder termination resistor is connected to
AGND. R is typically 11 kΩ.
VREF
R
R
R
R
2R
2R
2R
2R
2R
2R
RFB
DB11 DB10
(MSB)
DB9
DB1
DB0
(LSB)
OUT 1
AGND
Figure 1. Simplified D/A Circuit of AD7545
The binary weighted currents are switched between the OUT1
bus line and AGND by N-channel switches, thus maintaining a
constant current in each ladder leg independent of the switch
state.
The capacitance at the OUT1 bus line, COUT1, is code depen-
dent and varies from 70 pF (all switches to AGND) to 200 pF
(all switches to OUT1).
One of the current switches is shown in Figure 2. The input
resistance at VREF (Figure 1) is always equal to RLDR (RLDR is
the R/2R ladder characteristic resistance and is equal to value
“R”). Since RIN at the VREF pin is constant, the reference termi-
nal can be driven by a reference voltage or a reference current,
ac or dc, of positive or negative polarity. (If a current source is
used, a low temperature coefficient external RFB is recommended
to define scale factor.)
TO LADDER
FROM
INTERFACE
LOGIC
power supply. To minimize power supply currents it is recom-
mended that the digital input voltages be as close as practicably
possible to the supply rails (VDD and DGND).
The AD7545 may be operated with any supply voltage in the
range 5 ≤ VDD ≤ 15 volts. With VDD = +15 V the input logic
levels are CMOS compatible only, i.e., 1.5 V and 13.5 V.
BASIC APPLICATIONS
Figures 4 and 5 show simple unipolar and bipolar circuits using
the AD7545. Resistor R1 is used to trim for full scale. The
“G” versions (AD7545GLN, AD7545GCQ, AD7545GUD)
have a guaranteed maximum gain error of ± 1 LSB at +25°C
(VDD = +5 V), and in many applications it should be possible to
dispense with gain trim resistors altogether. Capacitor C1 provides
phase compensation and helps prevent overshoot and ringing when
using high speed op amps. Note that all the circuits of Figures 4, 5
and 6 have constant input impedance at the VREF terminal.
The circuit of Figure 1 can either be used as a fixed reference
D/A converter so that it provides an analog output voltage in the
range 0 to –VIN (note the inversion introduced by the op amp),
or VIN can be an ac signal in which case the circuit behaves as
an attenuator (2-Quadrant Multiplier). VIN can be any voltage
in the range –20 ≤ VIN + 20 volts (provided the op amp can
handle such voltages) since VREF is permitted to exceed VDD.
Table II shows the code relationship for the circuit of Figure 4.
VDD
R2*
18
20
C1
33pF
VDD
RFB
VIN
OUT1 1
VOUT
19 VREF AD7545
R1*
AGND 2
DGND
3
AD544L
(SEE TEXT)
ANALOG
COMMON
DB11–DB0
*REFER TO TABLE I
Figure 4. Unipolar Binary Operation
AGND
OUT 1
Figure 2. N-Channel Current Steering Switch
CIRCUIT INFORMATION—DIGITAL SECTION
Figure 3 shows the digital structure for one bit.
The digital signals CONTROL and CONTROL are generated
from CS and WR.
TO AGND SWITCH
VIN
TO OUT1 SWITCH
Table I. Recommended Trim Resistor Values vs. Grades for
VDD = +5 V
Trim
Resistor J/A/S
K/B/T
L/C/U GL/GC/GU
R1
500 Ω
200 Ω
100 Ω 20 Ω
R2
150 Ω
68 Ω
33 Ω
6.8 Ω
Table II. Unipolar Binary Code Table for Circuit of Figure 4
Binary Number in DAC Register Analog Output
INPUT BUFFERS
CONTROL
CONTROL
Figure 3. Digital Input Structure
The input buffers are simple CMOS inverters designed so that
when the AD7545 is operated with VDD = 5 V, the buffers con-
vert TTL input levels (2.4 V and 0.8 V) into CMOS logic levels.
When VIN is in the region of 2.0 volts to 3.5 volts, the input
buffers operate in their linear region and draw current from the
1111 1111
1000 0000
0000 0000
0000 0000
1111
0000
0001
0000
4095
–VIN 4096
2048
–VIN 4096 = –1/2 VIN
1
–VIN 4096
0 Volts
–4–
REV. A
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