8533AG-01LF データシートの表示（PDF） - Integrated Device Technology
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8533AG-01LF Datasheet PDF : 17 Pages
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8533-01 Data Sheet
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions Minimum
Typical
PCLK
IIH
Input High Current
nPCLK
VCC = VIN = 3.465V
VCC = VIN = 3.465V
PCLK
I
Input Low Current
IL
nPCLK
VCC = 3.465V, VIN = 0V
VCC = 3.465V, VIN = 0V
-5
-150
VPP
Peak-to-Peak Input Voltage
0.3
VCMR
Common Mode Input Voltage; NOTE 1, 2
VEE + 1.5
VOH
Output High Voltage; NOTE 3
VCC - 1.4
VOL
Output Low Voltage; NOTE 3
VCC - 2.0
VSWING Peak-to-Peak Output Voltage Swing
0.6
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications the maximum input voltage for PCLK and nPCLK is VCC + 0.3V.
NOTE 3: Outputs terminated with 50Ω to VCC - 2V.
Maximum
150
5
1
VCC
VCC - 0.9
VCC - 1.7
1.0
Units
µA
µA
µA
µA
V
V
V
V
V
TABLE 5. AC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
fMAX
tPD
tsk(o)
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
650
ƒ ≤ 650MHz
1.0
1.4
30
tsk(pp) Part-to-Part Skew; NOTE 3, 4
150
Buffer Additive Phase Jitter, RMS;
tjit
refer to Additive Phase Jitter section,
0.06
NOTE 5
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80% @ 50MHz
300
700
47
53
All parameters measured at 500MHz unless noted otherwise.
The cycle to cycle jitter on the input will equal the jitter on the output. The part does not add jitter.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 5: Driving only one input clock.
Units
MHz
ns
ps
ps
ps
ps
%
©2016 Integrated Device Technology, Inc
5
Revision F January 19, 2016
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