8533AG-01LF データシートの表示（PDF） - Integrated Device Technology

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8533AG-01LF

Low Skew, 1-to-4 Differential-to-3.3V LVPECL Fanout Buffer

Integrated Device Technology 

8533-01 Data Sheet

APPLICATION INFORMATION

WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS

Figure 2 shows how the differential input can be wired to accept

single ended levels. The reference voltage V_REF = VCC/2 is

generated by the bias resistors R1, R2 and C1. This bias circuit

should be located as close as possible to the input pin. The ratio

of R1 and R2 might need to be adjusted to position the V_REF

in the center of the input voltage swing. For example, if the input

clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V

and R2/R1 = 0.609.

FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT

TERMINATION FOR LVPECL OUTPUTS

The clock layout topology shown below is a typical termination

for LVPECL outputs. The two different layouts mentioned are

recommended only as guidelines.

FOUT and nFOUT are low impedance follower outputs that

generate ECL/LVPECL compatible outputs. Therefore, termi-

nating resistors (DC current path to ground) or current sources

must be used for functionality. These outputs are designed to

drive 50Ω transmission lines. Matched impedance techniques

should be used to maximize operating frequency and minimize

signal distortion. Figures 3A and 3B show two different layouts

which are recommended only as guidelines. Other suitable clock

layouts may exist and it would be recommended that the board

designers simulate to guarantee compatibility across all printed

circuit and clock component process variations.

FIGURE 3A. LVPECL OUTPUT TERMINATION

FIGURE 3B. LVPECL OUTPUT TERMINATION

©2016 Integrated Device Technology, Inc

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Revision F January 19, 2016

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