507M-01 データシートの表示（PDF） - Integrated Device Technology

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507M-01

PECL CLOCK SYNTHESIZER

Integrated Device Technology 

PECL CLOCK SYNTHESIZER

DATASHEET

ICS507-01

Description

The ICS507-01 is an inexpensive, simple way to

generate a low jitter 155.52 MHz (or other high speed)

differential PECL clock output from a low frequency

crystal input. Using Phase-Locked-Loop (PLL)

techniques, the devices use a standard fundamental

mode crystal to produce output clocks up to 200 MHz.

Stored in each chip’s ROM is the ability to generate a

selection of different multiples of the input reference

frequency, including an exact 155.52 MHz clock from

common crystals. For lowest jitter and phase noise on

a 155.52 MHz clock, a 19.44 MHz crystal and the x8

selection can be used.

This product is intended for clock generation. It has low

output jitter (variation in the output period), but input to

output skew and jitter are not defined nor guaranteed.

Features

• Packaged in 16 pin SOIC

• Available in Pb (lead) free package

• Input crystal frequency of 5 - 27 MHz

• Input clock frequency of 5 - 52 MHz

• Enable usage of common low-cost crystal

• Differential PECL output clock frequencies up to 200

MHz

• Duty cycle of 49/51

• Operation voltage of 3.3 V or 5.0 V (±5%)

• Ideal for SONET applications and oscillator

manufacturers

• Available in die form

• Industrial temperature versions available

• ICS507-02 is no longer available

Block Diagram

2

S0:1

X1/ICLK

Crystal or

clock input

X2

Clock

Buffer/

Crystal

Oscillator

VDD

1.1 kohm

RES

Clock

Synthesis

and Control

Circuitry

270 ohm

62 ohm

62 ohm

270 ohm

PECL

VDD

PECL

GND

Output Enable

(both outputs)

Output resistors shown are for unterminated lines. Refer to MAN09 for additional information.

IDT™ / ICS™ PECL CLOCK SYNTHESIZER

1

ICS507-01

REV I 041905

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