PCA8550 データシートの表示（PDF） - NXP Semiconductors.
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PCA8550 Datasheet PDF : 23 Pages
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NXP Semiconductors
PCA8550
4-bit multiplexed/1-bit latched 5-bit I2C EEPROM DIP switch
10. Dynamic characteristics
Table 8. Dynamic characteristics
Symbol Parameter
Conditions
Min
Typ
Max
Unit
tMPD
tSOV
tOVN
Mux input to output propagation delay
MUX_SELECT to output valid
OVERRIDE_N to NON_MUX output
delay
-
-
20
ns
-
-
22
ns
-
-
15
ns
tOVM
OVERRIDE_N to mux output delay
-
-
tr
rise time
output
1.0
-
tf
fall time
output
1.0
-
CL
load capacitance
test load on outputs
-
-
25
ns
3
ns/V
3
ns/V
15
pF
Table 9.
Symbol
fSCL
tHIGH
tLOW
tSP
tSU;DAT
tHD;DAT
tr
tf
tBUF
tSU;STA
tHD;STA
tSU;STO
Cb
Tcy(W)
I2C-bus dynamic characteristics
Parameter
SCL clock frequency
HIGH period of the SCL clock
LOW period of the SCL clock
pulse width of spikes that must be suppressed
by the input filter
data set-up time
data hold time
rise time of both SDA and SCL signals
fall time of both SDA and SCL signals
bus free time between a STOP and START
condition
set-up time for a repeated START condition
hold time (repeated) START condition
set-up time for STOP condition
capacitive load for each bus line
write cycle time[1]
Conditions
10 pF to 400 pF
bus
10 pF to 400 pF
bus
Min
Max
10
400
600
-
1.3
-
0
50
100
-
0
-
20
300
20
300
1.3
-
600
-
600
-
600
-
-
400
TYPICAL = 15
[1] WRITE CYCLE time can only be measured indirectly during write cycle. The device will not acknowledge its I2C address.
Unit
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
ms
11. Non-volatile storage specifications
Table 10. Non-volatile storage specifications
Parameter
Specification
memory cell data retention
10 years (minimum)
number of memory cell write cycles
100,000 cycles (minimum)
Application note AN250, “I2C DIP Switch” provides additional information on memory cell
data retention and the minimum number of write cycles.
PCA8550
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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