PCA8550 データシートの表示（PDF） - NXP Semiconductors.
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PCA8550 Datasheet PDF : 23 Pages
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NXP Semiconductors
PCA8550
4-bit multiplexed/1-bit latched 5-bit I2C EEPROM DIP switch
6.1 Function table
Table 4. Function table
OVERRIDE_N MUX_SELECT MUX_OUT OUTPUTS
0
0
All 0s
0
1
MUX_IN inputs
1
0
From non-volatile register
1
1
MUX_IN inputs
NON_MUXED_OUT
OUTPUT
All 0s
Latched NON_MUXED_OUT
From non-volatile register
From non-volatile register
[1] Latched NON_MUXED_OUT state will be the value present on the NON_MUXED_OUT output at the time
of the MUX_SELECT input transitioned from a logic 0 to a logic 1 state.
6.2 I2C-bus interface
Communicating with this device is initiated by sending a valid address on the I2C-bus. The
address format (see FIgure 2) is a fixed unique 7-bit value followed by a 1-bit read/write
value which determines the direction of the data transfer.
MSB
LSB
1 0 0 1 1 1 0 R/W
aaa-017628
Fig 5. I2C-bus address byte
Following the address and acknowledge bit are 8 data bits which, depending on the
read/write bit in the address, will read data from or write data to the non-volatile register.
Data will be written to the register if the read/write bit is logic 0 and the WP input is logic 0.
Data will be read from the register if the bit is logic 1. The three high-order bits (see
Figure 6) are logic 0. The next bit is data which is non-multiplexed. The low four bits are
the data which will be multiplexed. A write with any of the first three bits non-zero will be
aborted.
1. To ensure data integrity, the non-volatile register must be internally write protected
when VCC to the I2C-bus is powered down or VCC to the component is dropped below
normal operating levels.
PCA8550
Product data sheet
MSB
0
0
Fig 6. I2C-bus data byte
LSB
0
NON-
MUXED
DATA
MUX
DATA D
MUX
DATA C
MUX
DATA B
MUX
DATA A
aaa-017629
2. MUX_OUTx will be disabled when the master writes to PCA8550.
a. With WP enabled, during I2C write cycle the MUX_OUTx will be disabled after the
address acknowledge bit and the outputs will be enabled after the internal
EEPROM write is completed (Figure 7).
b. With WP disabled, during I2C write cycle the MUX_OUTx will be disabled after the
address acknowledge bit and enabled when there is a START condition on the
I2C-bus (Figure 8).
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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