PCA8550 データシートの表示（PDF） - NXP Semiconductors.
部品番号
コンポーネント説明
メーカー
PCA8550 Datasheet PDF : 23 Pages
| |||
NXP Semiconductors
PCA8550
4-bit multiplexed/1-bit latched 5-bit I2C EEPROM DIP switch
WP
I2C-bus
S ADDR + W A DATA = 00 A P
MUX_OUTx
MUX_OUTx output after EEPROM write cycle
Fig 7. Write when WP enabled
Internal EEPROM Write
Output on the ports
aaa-017630
WP
I2C-bus
S ADDR + W A DATA = FF A P
S
MUX_OUTx
Output disable
aaa-017631
Do not write to EEPROM when PW is HIGH, the MUX_OUTx will be disabled until another START condition on the I2C-bus
Fig 8. Write when WP disabled
6.3 Power-on reset
When power is applied to VCC, an internal power-on reset holds the PCA8550 in a reset
state until VCC has reached VPOR. At that point, the reset condition is released and the
PCA8550 volatile registers and I2C state machine will initialize to their default states.
The MUX_OUT and NON_MUXED_OUT pin values depend on:
• the OVERRIDE_N and MUX_SELECT logic levels
• the previously stored values in the EEPROM register/current MUX_IN pin values as
shown in Table 4.
PCA8550
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
7 of 23
Share Link: 