74LVT2952 データシートの表示（PDF） - NXP Semiconductors.
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74LVT2952 Datasheet PDF : 18 Pages
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NXP Semiconductors
74LVT2952
3.3 V Octal registered transceiver; 3-State
Table 8. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V). For test circuit, see Figure 8.
Symbol Parameter
Conditions
tsu(L)
th(H)
th(L)
tW
fmax
set-up time LOW An to CPAB or Bn to CPBA; see Figure 7
VCC = 2.7 V
VCC = 3.3 V 0.3 V
CEAB to CPAB or CEBA to CPBA; see Figure 7
hold time HIGH
VCC = 2.7 V
VCC = 3.3 V 0.3 V
An to CPAB or Bn to CPBA; see Figure 7
VCC = 2.7 V
VCC = 3.3 V 0.3 V
CEAB to CPAB or CEBA to CPBA; see Figure 7
hold time LOW
VCC = 2.7 V
VCC = 3.3 V 0.3 V
An to CPAB or Bn to CPBA; see Figure 7
VCC = 2.7 V
VCC = 3.3 V 0.3 V
CEAB to CPAB or CEBA to CPBA; see Figure 7
pulse width
VCC = 2.7 V
VCC = 3.3 V 0.3 V
CPAB or CPBA; HIGH or LOW; see Figure 5
VCC = 2.7 V
VCC = 3.3 V 0.3 V
maximum frequency CPBA, CPAB; VCC = 3.3 V 0.3 V; see Figure 5
[1] Typical values are measured at Tamb = 25 C and VCC = 3.3 V.
11. Waveforms
Tamb = 40 C to +85 C
Min
Typ[1]
Max
Unit
3.0
-
2.5
1.0
- ns
- ns
2.7
-
2.4
0.3
- ns
- ns
0.7
-
1.5
0.5
- ns
- ns
0.7
-
2.5
0.3
- ns
- ns
2.6
-
1.5
0.5
- ns
- ns
2.6
-
2.5
0
- ns
- ns
3.3
-
3.3
1.0
150
200
- ns
- ns
- MHz
VI
CPBA or
CPAB
GND
VOH
An or Bn
VOL
1/fmax
VM
tW
tW
tPHL
VM
VM
tPLH
VM
aaa-008847
See Table 9 for measurement points
Fig 5. Clock input to output propagation delay, clock pulse width and maximum frequency
74LVT2952
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 11 September 2013
© NXP B.V. 2013. All rights reserved.
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