M48Z2M1PL データシートの表示（PDF） - STMicroelectronics

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M48Z2M1PL

16 Mb (2Mb x 8) ZEROPOWER® SRAM

STMicroelectronics 

M48Z2M1, M48Z2M1Y

Table 2. Absolute Maximum Ratings (1)

Symbol

Parameter

Value

Unit

TA

Ambient Operating Temperature

0 to 70

°C

TSTG

Storage Temperature (VCC Off)

–40 to 85

°C

TBIAS

TSLD (2)

Temperature Under Bias

Lead Soldering Temperature for 10 seconds

–40 to 85

°C

260

°C

VIO

Input or Output Voltages

–0.3 to 7

V

VCC

Supply Voltage

–0.3 to 7

V

Notes: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a

stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational

section of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may

affect reliability.

2. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).

CAUTION: Negative undershoots below –0.3 volts are not allowed on any pin while in the Battery Back-up mode.

Table 3. Operating Modes

Mode

VCC

E

G

Deselect

VIH

X

4.75V to 5.5V

Write

or

VIL

X

Read

4.5V to 5.5V

VIL

VIL

Read

VIL

VIH

Deselect VSO to VPFD (min)

X

X

Deselect

≤ VSO

X

X

Notes: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage.

W

DQ0-DQ7

Power

X

High Z

Standby

VIL

DIN

Active

VIH

DOUT

Active

VIH

High Z

Active

X

High Z

CMOS Standby

X

High Z Battery Back-up Mode

Figure 2. DIP Pin Connections

NC

A20

A18

A16

A14

A12

A7

A6

A5

A4

A3

A2

A1

A0

DQ0

DQ1

DQ2

VSS

1

36

2

35

3

34

4

33

5

32

6

31

7

30

8

29

M48Z2M1

9 M48Z2M1Y 28

10

27

11

26

12

25

13

24

14

23

15

22

16

21

17

20

18

19

VCC

A19

NC

A15

A17

W

A13

A8

A9

A11

G

A10

E

DQ7

DQ6

DQ5

DQ4

DQ3

AI02049

Warning: NC = Not Connected.

DESCRIPTION (cont’d)

The M48Z2M1/2M1Y has its own Power-fail Detect

Circuit. The control circuitry constantly monitors the

single 5V supply for an out of tolerance condition.

When VCC is out of tolerance, the circuit write

protects the SRAM, providing a high degree of data

security in the midst of unpredictable system op-

erations brought on by low VCC. As VCC falls below

approximately 3V, the control circuitry connects the

batteries which sustain data until valid power re-

turns.

READ MODE

The M48Z2M1/2M1Y is in the Read Mode when-

ever W (Write Enable) is high and E (Chip Enable)

is low. The device architecture allows ripple-

through access of data from eight of 16,777,216

locations in the static storage array. Thus, the

unique address specified by the 21 Address Inputs

defines which one of the 2,097,152 bytes of data is

to be accessed. Valid data will be available at the

Data I/O pins within Address Access time (tAVQV)

after the last address input signal is stable, provid-

ing that the E (Chip Enable) and G (Output Enable)

access times are also satisfied. If the E and G

access times are not met, valid data will be avail-

2/12

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