M48Z2M1PL データシートの表示（PDF） - STMicroelectronics
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M48Z2M1PL Datasheet PDF : 12 Pages
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Figure 3. Block Diagram
M48Z2M1, M48Z2M1Y
VCC
POWER
2048K x 8
VOLTAGE SENSE
SRAM ARRAY
E
AND
SWITCHING
E
CIRCUITRY
INTERNAL
BATTERIES
VSS
A0-A20
DQ0-DQ7
W
G
AI02050
able after the later of Chip Enable Access time
(tELQV) or Output Enable Access Time (tGLQV). The
state of the eight three-state Data I/O signals is
controlled by E and G. If the outputs are activated
before tAVQV, the data lines will be driven to an
indeterminate state until tAVQV. If the Address In-
puts are changed while E and G remain low, output
data will remain valid for Output Data Hold time
(tAXQX) but will go indeterminate until the next Ad-
dress Access.
WRITE MODE
The M48Z2M1/2M1Y is in the Write Mode when-
ever W and E are active. The start of a write is
referenced from the latter occurring falling edge of
W or E. A write is terminated by the earlier rising
edge of W or E.
The addresses must be held valid throughout the
cycle. E or W must return high for minimum of tEHAX
from E or tWHAX from W prior to the initiation of
another read or write cycle. Data-in must be valid
tDVEH or tDVWH prior to the end of write and remain
valid for tEHDX or tWHDX afterward. G should be kept
high during write cycles to avoid bus contention;
although, if the output bus has been activated by a
low on E and G, a low on W will disable the outputs
tWLQZ after W falls.
Table 4. AC Measurement Conditions
Input Rise and Fall Times
Input Pulse Voltages
≤ 5ns
0 to 3V
Input and Output Timing Ref. Voltages 1.5V
Note that Output Hi-Z is defined as the point where data is no
longer driven.
Figure 4. AC Testing Load Circuit
5V
DEVICE
UNDER
TEST
1kΩ
1.9kΩ
OUT
CL = 100pF or 5pF
CL includes JIG capacitance
AI01030
3/12
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