M48Z128(2003) データシートの表示（PDF） - STMicroelectronics

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M48Z128
(Rev.:2003)

5.0V OR 3.3V, 1 Mbit (128 Kbit x 8) ZEROPOWER® SRAM

STMicroelectronics 

M48Z128, M48Z128Y, M48Z128V*

WRITE Mode

The M48Z128/Y/V is in the WRITE Mode whenev-

er W and E are active. The start of a WRITE is ref-

erenced from the latter occurring falling edge of W

or E. A WRITE is terminated by the earlier rising

edge of W or E.

The addresses must be held valid throughout the

cycle. E or W must return high for minimum of

tEHAX from E or tWHAX from W prior to the initiation

of another READ or WRITE cycle. Data-in must be

valid tDVWH prior to the end of WRITE and remain

valid for tWHDX or tEHDX afterward. G should be

kept high during WRITE cycles to avoid bus con-

tention; although, if the output bus has been acti-

vated by a low on E and G, a low on W will disable

the outputs tWLQZ after W falls.

Figure 9. WRITE Enable Controlled, WRITE AC Waveforms

A0-A16

E

tAVEL

tAVWL

tAVAV

VALID

tAVWH

tWLWH

W

DQ0-DQ7

tWLQZ

tWHDX

DATA INPUT

tDVWH

Note: Output Enable (G) = High.

tWHAX

tWHQX

AI01198

Figure 10. Chip Enable Controlled, WRITE AC Waveforms

A0-A16

E

tAVEL

tAVWL

tAVAV

VALID

tAVEH

tELEH

tEHAX

W

tEHDX

DQ0-DQ7

DATA INPUT

Note: Output Enable (G) = High.

tDVEH

AI01199

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