82C52 データシートの表示（PDF） - Renesas Electronics

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82C52

CMOS Serial Controller Interface

Renesas Electronics 

82C52

UART Timing Characterization (Continued)

NOTES:

1. TBRE bit D6 in USR is updated each time TBRE changes state.

2. A. With TR initially empty, TCLTH(TBRE) occurs from the 4th falling edge of CO(BRG) after WR goes high.

B. With TR initially full, TCLTH(TBRE) occurs from the trailing edge of the 15th CO(BRG) in the last Stop bit provided WR went high by the

trailing edge of the 12th CO(BRG) in the last Stop bit.

3. A. With TR (Transmitter Register) initially empty, TDTX occurs from the 5th falling edge of CO(BRG) after WR goes high.

B. With TR initially full, TDTX occurs from the trailing edge of the 16th CO(BRG) in the last Stop bit provided WR went high by the trailing edge

of the 12th CO(BRG) in the last Stop bit.

4. TCTHX is time before end of last Stop bit by which CTS must be inactive (high) to prevent transmission of the character waiting in TBR.

5. With CTS high (disable transmit) and TBR full, TCLTH(TBRE) occurs from the 4th falling edge of CO(BRG) after CTS goes low.

6. With CTS high (disable transmit) and TBR full, TDTX occurs from the 5th falling edge of CO(BRG) after CTS goes low.

11

12

13

14

15

16

1/I

2/I

3/I

CO(BRG)

SDI

RD

(25)

TDRH

DR NOTE 1

INTR NOTE 2

LAST STOP BIT

RBR

(26)

TRLDL

(21)

TIHF

START BIT / IDLE

USR

(23)

TRLIL

FIGURE 19. RECEIVE TIMING

FN2950 Rev 4.00

November 25, 2015

Page 17 of 21

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