82C52 データシートの表示（PDF） - Renesas Electronics

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82C52

CMOS Serial Controller Interface

Renesas Electronics 

82C52

UART Timing Characterization (Continued)

WR

RTS/DTR

MCR

(27)

TWHO

RD

MSR

DSR/CTS

INTR NOTE 3

(22)

TIHM

(23)

TRLIL

FIGURE 20. OTHER TIMING

NOTES:

1. DR bit D7 in USR is updated each time DR changes state. TDRH always from trailing edge of 11th CO(BRG) in last Stop bit.

2. INTR on receive flags OE, FE, PE, and RBRK: INTEN enabled; Respective USR bits updated at this time regardless of interrupt configuration.

- INT on OE, FE, PE, RBRK occurs from the trailing edge of the 11th CO(BRG) in the last Stop bit. To avoid OE, RD(RBR) must go low by the

trailing edge of the 8th CO(BRG) in the last Stop bit.

3. INTR on MS: INTEN and MIEN enabled; USR bit D4(MS) is updated at this time regardless of INTEN/MIEN.

- INTR on MS occurs whenever CTS or DSR input changes state.

FN2950 Rev 4.00

November 25, 2015

Page 18 of 21

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