AD7740(2000) データシートの表示（PDF） - Analog Devices
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AD7740 Datasheet PDF : 11 Pages
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AD7740 SPECIFICATIONS (VDD = 3.0 V to 3.6 V, 4.75 V to 5.25 V, GND = 0 V, REFIN = 2.5 V; CLKIN = 1 MHz; All
specifications TMIN to TMAX unless otherwise noted.)
Parameter2
K, Y Versions1
Min Typ Max
Unit
Test Conditions/Comments
DC PERFORMANCE
Integral Nonlinearity
CLKIN = 32 kHz3
CLKIN = 1 MHz
CLKIN = 32 kHz3
CLKIN = 1 MHz
Offset Error
Gain Error
Offset Error Drift3
Gain Error Drift3
Power Supply Rejection Ratio3
± 0.012
± 0.012
± 0.018
± 0.018
±7
± 35
±7
± 35
± 0.1 ± 0.7
± 20
±4
–55
–65
% of Span4
% of Span
% of Span
% of Span
mV
mV
% of Span
µV/°C
ppm of Span/°C
dB
dB
Unbuffered Mode, External Clock at CLKIN
Unbuffered Mode, Crystal at CLKIN
Buffered Mode, External Clock at CLKIN
Buffered Mode, Crystal at CLKIN
Unbuffered Mode, VIN = 0 V
Buffered Mode, VIN = 0.1 V
∆VDD = ± 5% (5 V)
∆VDD = ± 10% (3.3 V)
ANALOG INPUT, VIN
Nominal Input Span
Input Current
0 – VREF
V
0.1
VDD – 0.2 V
8
10
µA
5
100
nA
± 150 mV Overrange Available
Buffered Mode
Unbuffered Mode, VIN = 5.4 V, REFIN = 5.25 V
Buffered Mode, VIN = 0.1 V, REFIN = 2.5 V
REFERENCE VOLTAGE
REFIN5
Nominal Input Voltage
REFOUT
Output Voltage
Output Impedance3
Reference Drift3
Line Rejection3
Line Rejection3
Reference Noise (0.1 Hz to 10 Hz)3
2.5
VDD
2.3
2.5
2.7
1
± 50
–75
–60
100
V
V
kΩ
ppm/°C
dB
dB
µV p–p
See Pin Function Description
∆VDD = ± 5% (5 V)
∆VDD = ± 10% (3.3 V)
FOUT OUTPUT
Nominal Frequency Span
LOGIC INPUTS (CLKIN, BUF)3
CLKIN
Input frequency
Input High Voltage, VIH
Input High Voltage, VIH
Input Low Voltage, VIL
Input Low Voltage, VIL
Input Current
Pin Capacitance
BUF
Input High Voltage, VIH
Input High Voltage, VIH
Input Low Voltage, VIL
Input Low Voltage, VIL
Input Current
Pin Capacitance
0.1 fCLKIN to 0.9 fCLKIN
Hz
32
3.5
2.5
3
2.4
2.1
3
1000
kHz
V
V
0.8
V
0.4
V
±2
µA
10
pF
V
V
0.8
V
0.4
V
± 100
nA
10
pF
VIN = 0 V to VREF. See Figure 2
For Specified Performance
VDD = 5 V ± 5%
VDD = 3.3 V ± 10%
VDD = 5 V ± 5%
VDD = 3.3 V ± 10%
VIN = 0 V to VDD
VDD = 5 V ± 5%
VDD = 3.3 V ± 10%
VDD = 5 V ± 5%
VDD = 3.3 V ± 10%
LOGIC OUTPUTS (FOUT, CLKOUT)3
Output High Voltage, VOH
Output High Voltage, VOH
Output Low Voltage, VOL
4.0
V
2.1
V
0.1
0.4
V
Output Sourcing 200 µA6. VDD = 5 V ± 5%
Output Sourcing 200 µA6. VDD = 3.3 V ± 10%
Output Sinking 1.6 mA6
POWER REQUIREMENTS
VDD7
IDD (Normal Mode)8
IDD (Normal Mode)8
IDD (Power-Down)
Power-Up Time3
3.0
5.25
V
0.9
1.25
mA
1.1
1.5
mA
30
100
µA
30
µs
VIH = VDD, VIL= GND. Unbuffered Mode
VIH = VDD, VIL= GND. Buffered Mode
Exiting Power-Down (Ext. Clock at CLKIN)
NOTES
1Temperature range: K Version, 0°C to +85°C; Y Version, –40°C to +105°C; typical specifications are at 25°C.
2See Terminology.
3Guaranteed by design and characterization, not production tested.
4Span = Max output frequency–Min output frequency.
5Because this pin is bidirectional, any external reference must be capable of sinking/sourcing 400 µA in order to overdrive the internal reference.
6These logic levels apply to CLKOUT only when it is loaded with one CMOS load.
7Operation at VDD = 2.7 V is also possible with degraded specifications.
8Outputs unloaded. IDD increases by CL × VOUT × fFOUT when FOUT is loaded. If using a crystal/resonator as the clock source, IDD will vary depending on the crystal/resonator
type (see Clock Generation section).
Specifications subject to change without notice.
–2–
REV. 0
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