AD842 データシートの表示（PDF） - Analog Devices
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AD842 Datasheet PDF : 17 Pages
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Data Sheet
THEORY OF OPERATION
OFFSET NULLING
The input offset voltage of the AD842 is very low for a high
speed op amp, but if additional nulling is required, the circuit
shown in Figure 28 can be used.
SETTLING TIME
Figure 29 and Figure 31 show the settling performance of the
AD842 in the test circuit shown in Figure 30.
Settling time is the interval of time from the application of an
ideal step function input until the closed-loop amplifier output
enters and remains within a specified error band.
This definition encompasses the major components that
comprise settling time. They include the following:
• Propagation delay through the amplifier.
• Slewing time to approach the final output value.
• Time of recovery from the overload associated with
slewing.
• Linear settling to within the specified error band.
Expressed in these terms, the measurement of settling time
must be accurate to assure the user that the amplifier is worth
consideration for the application.
+VS
10kΩ
0.1µF
3
13
2.2µF
4
11
VIN AD842 10
5
6
0.1µF
VOUT
RL
2.2µF
–VS
Figure 28. Offset Nulling (PDIP)
AD842
100%
90%
10V
10mV
20ns
OUTPUT:
10V/DIV
OUTPUT
ERROR:
0.02%/DIV
10%
0%
Figure 29. 0.01% Settling Time
Figure 30 shows how measurement of the AD842 0.01% settling
in 100 ns is accomplished by amplifying the error signal from a
false summing junction with a very high speed proprietary
hybrid error amplifier specially designed to enable testing of
small settling errors. Under test, the device drives a 300 Ω load.
The input to the error amp is clamped to avoid possible
problems associated with the overdrive recovery of the
oscilloscope input amplifier. The error amp gains the error from
the false summing junction by 15, and it contains a gain vernier
to fine trim the gain.
Figure 31 shows the long-term stability of the settling
characteristics of the AD842 output after a 10 V step. There is
no evidence of settling tails after the initial transient recovery
time. The use of a junction isolated process, together with
careful layout, avoids these problems by minimizing the effects
of transistor isolation capacitance discharge and thermally
induced shifts in circuit operating points. These problems do
not occur even under high output current conditions.
DDD5109
FLAT-TOP
PULSE
GENERATOR
499Ω
499Ω
50Ω
499Ω
ERROR
AMP
(×15)
HP6263
TEK
7A13
TEK
7A16
TEK
7603
OSCILLOSCOPE
1kΩ
1kΩ
+15V
0.1µF
2.2µF
11
4
AD842
5
6
10
0.1µF
2.2µF
–15V
FET PROBE
TEK P6201
499Ω
Figure 30. Settling Time Test Circuit (PDIP)
Rev. F | Page 9 of 16
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