ADG465 データシートの表示（PDF） - Analog Devices
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ADG465 Datasheet PDF : 12 Pages
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ADG465
Data Sheet
When a negative overvoltage is applied to the channel protector
circuit, the PMOS transistor enters a saturated mode of operation
as the drain voltage exceeds VSS − VTP (see Figure 18). As in the
case of the positive overvoltage, the other MOS devices are in a
nonsaturated mode of operation.
The channel protector is also functional when the supply
rails are down (for example, power failure) or momentarily
unconnected (for example, rack system). The channel protector is
in the off high impedance state with no supply rail voltage applied,
this known power supply state is where the channel protector has
an advantage over more conventional protection methods, such
as diode clamping (see the Applications Information section).
When VDD and VSS equal 0 V, all transistors are off, and the
current is limited to microampere levels (see Figure 19).
TRENCH ISOLATION
The MOS devices that make up the channel protector are isolated
from each other by an oxide layer (trench, see Figure 17). When
the NMOS and PMOS devices are not electrically isolated from
each other, there is a latch-up possibility caused by parasitic
junctions between complementary metal-oxide semiconductor
(CMOS) transistors. Latch up is caused when PN junctions that
are normally reverse biased become forward biased, causing
large currents to flow, which can be destructive.
CMOS devices are normally isolated from each other by junction
isolation. In junction isolation, the N and P wells of the CMOS
transistors form a diode that is reverse biased under normal
operation. However, during overvoltage conditions, this diode
becomes forward biased. Two transistors form a silicon-controlled
rectifier (SCR) type circuit, causing a significant amplification
of the current that, in turn, leads to latch up. With trench isolation,
this diode is removed, resulting in a latch-up proof circuit.
VG
VS
VD
VG
VS
VD
T
P+
P-CHANNEL
P+
T
N+
N-CHANNEL
N+
T
R
R
R
E
E
E
N
N
N
C
H
N–
C
H
P–
C
H
BURIED OXIDE LAYER
SUBSTRATE (BACKGATE)
Figure 17. Trench Isolation
NEGATIVE
OVERVOLTAGE
(–20V)
VSS – VTP*
(–13V)
NEGATIVE
OVERVOLTAGE
(–20V)
NMOS
PMOS
NMOS
NONSATURATED SATURATED
NONSATURATED
VDD (+15V)
VSS (–15V)
VDD (+15V)
*VTP = PMOS THRESHOLD VOLTAGE (+2V)
Figure 18. Negative Overvoltage on the Channel Protector
0V
POSITIVE OR
NEGATIVE
OVERVOLTAGE
NMOS
OFF
PMOS
OFF
NMOS
OFF
VDD (0V)
VSS (0V)
VDD (0V)
Figure 19. Channel Protector Supplies Equal to 0 V
Rev. C | Page 10 of 12
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