ADG465 データシートの表示（PDF） - Analog Devices

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ADG465

Single Channel Protector in a SOT-23 Package and a MSOP Package

Analog Devices 

Data Sheet

ADG465

THEORY OF OPERATION

Figure 14 shows a simplified schematic of a channel protector

circuit. The circuit is comprised of four metal-oxide semiconductor

(MOS) transistors: two negative metal-oxide semiconductor

(NMOS) and two positive metal-oxide semiconductor (PMOS).

One of the PMOS devices does not lie directly in the signal path;

however, it connects the source of the second PMOS device to

its back gate, which has the effect of lowering the threshold voltage

and increasing the input signal range of the channel for normal

operation. The source and back gate of the NMOS devices are

connected for the same reason. During normal operation, the

channel protectors have a resistance of 80 Ω typical. The channel

protectors are low power devices; even under fault conditions,

the supply current is limited to submicroampere levels. All

transistors are dielectrically isolated from each other using

trench isolation. Using trench isolation makes it impossible to

latch up the channel protectors. For further details, see the

Trench Isolation section.

VSS

NMOS

PMOS

NMOS

PMOS

VDD

VSS

VDD

Figure 14. Channel Protector Circuit Schematic

OVERVOLTAGE PROTECTION

When a fault condition occurs on the input of a channel protector,

the voltage on the input exceeds some threshold voltage set by

the supply rail voltages. The threshold voltages (VTP and VTN)

are related to the supply rails. For a positive overvoltage, the

threshold voltage is given by VDD − VTN, where VTN is the threshold

voltage of the NMOS transistor (1.5 V typical). For a negative

overvoltage, the threshold voltage is given by VSS − VTP, where

VTP is the threshold voltage of the PMOS device (1.5 V typical).

If the input voltage exceeds these threshold voltages, the output

of the channel protector (with no load) is clamped at these

threshold voltages. However, the channel protector output

clamps at a voltage inside these thresholds if the output is loaded.

For example, with an output load of 1 kΩ, VDD = 15 V and a

positive overvoltage. The output clamps at VDD − VTN − ΔV = 15

V − 1.5 V − 0.6 V = 12.9 V, where ΔV is due to IR voltage drops

across the channels of the MOS devices (see Figure 16). As

shown in Figure 16, the current during fault condition is

determined by the load on the output (that is, VCLAMP/RL).

However, if the supplies are off, the fault current is limited to

the nanoampere level.

Figure 15, Figure 18, and Figure 19 show the operating

conditions of the signal path transistors during various fault

conditions. Figure 15 shows how the channel protectors operate

when a positive overvoltage is applied to the channel protector.

The first NMOS transistor goes into a saturated mode of

operation as the voltage on its drain exceeds the gate voltage

(VDD) − the threshold voltage, VTN (see Figure 16). The potential

at the source of the NMOS device is equal to VDD − VTN. The

other MOS devices are in a nonsaturated mode of operation.

VDD – VTN*

(+13.5V)

POSITIVE

OVERVOLTAGE

(+20V)

NMOS

PMOS

NMOS

SATURATED

NONSATURATED

NONSATURATED

VDD (+15V)

VSS (–15V)

VDD (+15V)

*VTN = NMOS THRESHOLD VOLTAGE (+1.5V)

Figure 15. Positive Overvoltage on the Channel Protector

VD

(+20V)

VG

VS

(VDD = +15V)

(+13.5V)

ΔV

PMOS

NMOS

OVERVOLTAGE

OPERATION

(SATURATED)

N+

EFFECTIVE

SPACE CHARGE

REGION

VT = 1.5V

P–

N+

N+

N-CHANNEL

(VG – VT = 13.5V)

NONSATURATED

OPERATION

IOUT

RL VCLAMP

NOTES

1. VD IS THE VOLTAGE AT THE DRAIN OF THE SWITCH, VG IS THE VOLTAGE AT THE

GATE OF THE SWITCH, AND VS IS THE VOLTAGE AT THE SOURCE OF THE SWITCH.

Figure 16. Negative Overvoltage Operation on the Channel Protector

Rev. C | Page 9 of 12

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