SN74LS161AN データシートの表示（PDF） - ON Semiconductor
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SN74LS161AN Datasheet PDF : 8 Pages
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SN74LS161A, SN74LS163A
CONNECTION DIAGRAM DIP (TOP VIEW)
VCC TC Q0 Q1 Q2 Q3 CET PE
16 15 14 13 12 11 10 9
1 2 3 4 56 78
*R CP P0 P1 P2 P3 CEP GND
NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual In-Line Package.
*MR for LS161A
*SR for LS163A
PIN NAMES
PE
P0 − P3
CEP
CET
CP
MR
SR
Q0 − Q3
TC
Parallel Enable (Active LOW) Input
Parallel Inputs
Count Enable Parallel Input
Count Enable Trickle Input
Clock (Active HIGH Going Edge) Input
Master Reset (Active LOW) Input
Synchronous Reset (Active LOW) Input
Parallel Outputs
Terminal Count Output
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW.
LOADING (Note a)
HIGH
LOW
1.0 U.L.
0.5 U.L.
0.5 U.L.
1.0 U.L.
0.5 U.L.
0.5 U.L.
1.0 U.L.
10 U.L.
10 U.L.
0.5 U.L.
0.25 U.L.
0.25 U.L.
0.5 U.L.
0.25 U.L.
0.25 U.L.
0.5 U.L.
5 U.L.
5 U.L.
LOGIC SYMBOL
934 56
PE P0 P1 P2 P3
7
CEP
10
CET
TC
15
2
CP
*R Q0 Q1 Q2 Q3
1 14 13 12 11
VCC = PIN 16
GND = PIN 8
*MR for LS161A
*SR for LS163A
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