SN74LS161AN データシートの表示（PDF） - ON Semiconductor
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SN74LS161AN Datasheet PDF : 8 Pages
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SN74LS161A, SN74LS163A
AC WAVEFORMS (continued)
COUNT ENABLE TRICKLE INPUT
TO TERMINAL COUNT OUTPUT DELAYS
CET
The positive TC pulse occurs when the outputs are in the (Q0
• Q1 • Q2 • Q3) state for the LS161 and LS163.
TC
Figure 3.
1.3 V
1.3 V
tPLH
1.3 V
tPHL
1.3 V
OTHER CONDITIONS: CP = PE = CEP = MR = H
CLOCK TO TERMINAL COUNT DELAYS
CP
The positive TC pulse is coincident with the output state
(Q0 • Q1 • Q2 • Q3) for the LS161 and LS163.
TC
Figure 4.
1.3 V
tPLH
1.3 V
1.3 V
1.3 V
tPHL
1.3 V
OTHER CONDITIONS: PE = CEP = CET = MR = H
SETUP TIME (ts) AND HOLD TIME (th)
FOR PARALLEL DATA INPUTS
The shaded areas indicate when the input is permitted to
change for predictable output performance.
CP
ts(H)
P0 w P1 w P2 w P3
Q0 w Q1 w Q2 w Q3
Figure 5.
1.3 V
th(H) = 0 ts(L)
1.3 V
1.3 V
1.3 V
th(L) = 0
1.3 V
OTHER CONDITIONS: PE = L, MR = H
SETUP TIME (ts) AND HOLD TIME (th) FOR
COUNT ENABLE (CEP) AND (CET) AND
PARALLEL ENABLE (PE) INPUTS
The shaded areas indicate when the input is permitted to
change for predictable output performance.
CP
ts(L)
SR or PE
1.3 V
th (L) = 0
ts(H)
1.3 V
th(H) = 0
CP
ts(H)
1.3 V
1.3 V
CEP
PARALLEL LOAD
(See Fig. 5)
COUNT MODE
(See Fig. 7)
ts(H)
Q RESPONSE TO PE
RESET
COUNT OR LOAD
CET 1.3 V
Q RESPONSE TO SR
Q
Figure 6.
1.3 V
ts(L)
th(H) = 0
1.3 V
th(H) = 0
1.3 V
COUNT
1.3 V
th(L) = 0
1.3 V
ts(L)
1.3 V
HOLD
OTHER CONDITIONS: PE = H, MR = H
Figure 7.
1.3 V
th(L) = 0
1.3 V
HOLD
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