24C02SI データシートの表示（PDF） - Unspecified
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24C02SI Datasheet PDF : 8 Pages
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Turbo IC, Inc.
24C01/24C02
PRODUCT INTRODUCTION
DEVICE ADDRESSING:
Following the start condition, the master will issue a device
address byte consisting of 1010 (A2) (A1) (A0) (R/W) to ac-
cess the selected Turbo IC 24C01/24C02 for a read or write
operation. A0, A1, and A2 are the device address select bits
which have to match the A0, A1, and A2 pin inputs on the
24C01/24C02 device. The B[7] bit (B[6] bit in the 24C01) is
the most significant bit of the memory address. The (R/W)
bit is a high (1) for read and low (0) for write. If A0, A1, or
A2 are left unconnected, the Turbo IC 24C01/24C02 device
shall interpret as V input(s).
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DATA INPUT DURING WRITE OPERATION:
During the write operation, the Turbo IC 24C01/24C02 latches
the SDA bus signal on the rising edge of the SCL clock.
DATA OUTPUT DURING READ OPERATION:
During the read operation, the Turbo IC 24C01/24C02 seri-
ally shifts the data onto the SDA bus on the falling edge of
the SCL clock.
MEMORY ADDRESSING:
The memory address is sent by the master in the form of 2
bytes. Device address A2, A1, and A0 is included in the first
byte.The remaining memory address bits B[7:0] are included
in the second byte of the device address of the 24C02. The
memory address byte can only be sent as part of a write
operation. On the other hand, in the 24C01, the first byte is
the same as in the 24C02; however, the second byte of the
24C01 contains remaining address bits B[6:0]. The B[7] bit
in the 24C01 is treated as a 'don't care' bit.
BYTE WRITE OPERATION:
The master initiates the byte write operation by issuing a
start condition, followed by the device address byte 1010
(A2) (A1) (A0) 0, followed by the memory address byte, fol-
lowed by one data byte, followed by an acknowledge, then a
stop condition. After each byte transfer, the Turbo IC 24C01/
24C02 acknowledges the successful data transmission by
pulling the SDA bus low. The stop condition starts the inter-
nal EEPROM write cycle, and all inputs are disabled until the
completion of the write cycle.
PAGE WRITE OPERATION:
The master initiates the page write operation by issuing a
start condition, followed by the device address byte 1010
(A2) (A1) (A0) 0, followed by the memory address byte, fol-
lowed by up to 8 data bytes, followed by an acknowledge,
then a stop condition. After each byte transfer, the Turbo IC
24C01/24C02 acknowledges the successful data transmis-
sion by pulling SDA low. After each data byte transfer, the
memory address counter is automatically incremented by
one. The stop condition starts the internal EEPROM write
cycle only if the stop condition occurs in the clock cycle im-
mediately following the acknowledge (10th clock cycle). All
inputs are disabled until the completion of the write cycle.
POLLING ACKNOWLEDGE:
During the internal write cycle of a write operation in the Turbo
IC 24C01/24C02, the completion of the write cycle can be
detected by polling acknowledge.The master starts acknowl-
edge polling by issuing a start condition, then followed by the
device address byte 1010 (A2) (A1) (A0) 0. If the internal
write cycle is finished, the Turbo IC 24C01/24C02 acknowl-
edges by pulling the SDA bus low. If the internal write cycle is
still ongoing, the Turbo IC 24C01/24C02 does not acknowl-
edge because it’s inputs are disabled. Therefore, the device
will not respond to any command. By using polling acknowl-
edge, the system delay for write operations can be reduced.
Otherwise, the system needs to wait for the maximum inter-
nal write cycle time, tWC, given in the spec.
POWER ON RESET:
The Turbo IC 24C01/24C02 has a Power On Reset circuit
(POR) to prevent data corruption and accidental write op-
erations during power up. On power up, the internal reset
signal is on and the Turbo IC 24C01/24C02 will not respond
to any command until the VCC voltage has reached the POR
threshold value.
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