WRITE CYCLE 2 (E Controlled, See Notes 1 and 2)
6227A–20
6227A–25
6227A–35
6227A–45
Parameter
Symbol Min Max Min Max Min Max Min Max Unit Notes
Write Cycle Time
tAVAV
20
—
25
—
35
—
45
—
ns
3
Address Setup Time
Address Valid to End of Write
Enable to End of Write
tAVEL
0
—
0
—
0
—
0
—
ns
tAVEH
15
—
17
—
20
—
25
—
ns
tELEH,
15
—
17
—
20
—
25
—
ns
4, 5
tELWH
Write Pulse Width
Data Valid to End of Write
tWLEH
15
—
17
—
20
—
25
—
ns
tDVEH
10
—
10
—
15
—
20
—
ns
Data Hold Time
tEHDX
0
—
0
—
0
—
0
—
ns
Write Recovery Time
tEHAX
0
—
0
—
0
—
0
—
ns
NOTES:
1. A write occurs during the overlap of E low and W low.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus con-
tention conditions during read and write cycles.
3. All timings are referenced from the last valid address to the first transitioning address.
4. If E goes low coincident with or after W goes low, the output will remain in a high–impedance state.
5. If E goes high coincident with or before W goes high, the output will remain in a high–impedance state.
A (ADDRESS)
E (CHIP ENABLE)
W (WRITE ENABLE)
D (DATA IN)
Q (DATA OUT)
WRITE CYCLE 2 (E Controlled See Notes 1 and 2)
tAVAV
tAVEH
tELEH
tAVEL
tWLEH
tELWH
tDVEH
DATA VALID
HIGH–Z
tEHAX
tEHDX
Motorola Memory Prefix
Part Number
ORDERING INFORMATION
(Order by Full Part Number)
MCM 6227A WJ XX XX
Shipping Method (R2 = Tape and Reel, Blank = Rails)
Speed (20 = 20 ns, 25 = 25 ns, 35 = 35 ns, 45 = 45 ns)
Package (WJ = 400 mil SOJ)
Full Part Numbers — MCM6227AWJ20
MCM6227AWJ25
MCM6227AWJ35
MCM6227AWJ45
MCM6227AWJ20R2
MCM6227AWJ25R2
MCM6227AWJ35R2
MCM6227AWJ45R2
MCM6227A
6
MOTOROLA FAST SRAM