SI5341C-A-GM データシートの表示（PDF） - Silicon Laboratories

部品番号

コンポーネント説明

メーカー

SI5341C-A-GM

LOW-JITTER, 10-OUTPUT, ANY-FREQUENCY, ANY-OUTPUT CLOCK GENERATOR

Silicon Laboratories 

Si5341/40

Table 7. LVCMOS Clock Output Specifications (Continued)

(VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 85 °C)

Parameter

Symbol

Output Voltage Low1, 2, 3 VOL

Test Condition

CMOS1

CMOS2

CMOS3

IOL = 10 mA

IOL = 12 mA

IOL = 17 mA

CMOS1

CMOS2

CMOS3

IOH = -6 mA

IOL = 8 mA

IOL = 11 mA

LVCMOS Rise and Fall

Times3

(20% to 80%)

CMOS1 IOH = –3 mA

CMOS2 IOH = –4 mA

CMOS3

IOL = 5 mA

tr/tf

VDDO = 3.3V

VDDO = 2.5 V

VDDO = 1.8 V

Min

Typ

VDDO = 3.3 V

—

—

—

—

—

—

VDDO = 2.5 V

—

—

—

—

—

—

VDDO = 1.8 V

—

—

—

—

—

—

—

360

—

420

—

280

Max

Units

VDDO x 0.15 V

VDDO x 0.15 V

VDDO x 0.15 V

—

ps

—

ps

—

ps

Notes:

1. Driver strength is a register programmable setting and stored in NVM. Options are CMOS1, CMOS2, CMOS3.

2. IOL/IOH is measured at VOL/VOH as shown in the DC test configuration

3. A series termination resistor (Rs) is recommended to help match the source impedance to a 50 Ohm PCB trace. A 5 pF

capacitive load is assumed.

DC Test Configuration

Zs

VOL/VOH

IOL/IOH

AC Test Configuration

Zs

Rs

50

Zs + Rs = 50 Ohms

5 pF

Preliminary Rev. 0.9

11

Share Link: