ISL88013IH546Z-TK データシートの表示（PDF） - Renesas Electronics
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ISL88013IH546Z-TK
Renesas Electronics
ISL88013IH546Z-TK Datasheet PDF : 15 Pages
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ISL88011, ISL88012, ISL88013, ISL88014, ISL88015
Manual Reset
The manual reset input (MR) allows the user to trigger a reset
by using a push-button switch. The MR input is an active-low
debounced input. By connecting a push-button directly from
MR to ground, the designer adds manual system reset
capability (see Figure 4). Reset is asserted if the MR pin is
pulled low to less than 100mV for 1µs or longer while the push-
button is closed. After MR is released, the reset outputs remain
asserted for tPOR (200ms) and then released.
VDD
ISL88011
ISL88012
ISL88013
ISL88014
ISL88015
Rpu
RST/MR
PB
FIGURE 4. CONNECTING A MANUAL RESET PUSH-BUTTON
Watchdog Timer
The Watchdog Timer circuit checks microprocessor activity by
monitoring the WDI input pin. The microprocessor must
periodically toggle the WDI pin within tWDT (1.6s nominal),
otherwise the reset signal is asserted (see Figure 5). Internally,
the 1.6s timer is cleared by either a reset or by toggling the
WDI input.
Besides the 1.6s default timeout during normal operation,
these devices also have a longer 51s timeout for start-up.
During this time, a reset cannot be asserted due to the WDI not
being toggled. The longer delay at power-on allows an
operating system to boot, an FPGA to initialize, or the system
software to initialize without the burden of dealing with the
Watchdog.
Symbol Table
WAVEFORM
INPUTS
Must be
steady
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
OUTPUTS
Will be
steady
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Changing:
State Not
Known
Center Line
is High
Impedance
VDD
VTHVDD
1V
WDI
START tWDT
<tWDT
<tWDT
tWDT
STARTtWDT
RST
tPOR
>tWDPS
tPOR
RST
FIGURE 5. WATCHDOG TIMING DIAGRAM
FN8093 Rev 5.00
December 4, 2015
Page 10 of 15
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