ISL88013IH546Z-TK データシートの表示（PDF） - Renesas Electronics

部品番号

コンポーネント説明

メーカー

ISL88013IH546Z-TK

5 Ld Voltage Supervisors with Adjustable Power-On Reset, Dual Voltage Monitoring or Watchdog Timer Capability

Renesas Electronics 

ISL88011, ISL88012, ISL88013, ISL88014, ISL88015

Principles of Operation

The ISL88011, ISL88012, ISL88013, ISL88014, ISL88015

devices provide those functions needed for critical voltage

monitoring. These features include Power-On Reset control,

customizable supply voltage supervision, Watchdog Timer

capability, and manual reset assertion. By integrating all of

these features into a small 5 Ld SOT-23 package and using

only 5.5µA of supply current, the ISL88011, ISL88012,

ISL88013, ISL88014, ISL88015 devices can assist in lowering

system cost, reducing board space requirements, and

increasing the reliability of a system.

Low Voltage Monitoring

During normal operation, these supervisors monitor both the

voltage level of VDD (ISL88011, ISL88012, ISL88013) and/or

VMON (ISL88012, ISL88014, ISL88015). The device asserts a

reset if any of these voltages falls below their respective trip

points. The reset signal effectively prevents the system from

operating during a power failure or brownout condition. This

reset signal remains asserted until VDD and the voltage on

VMON exceed their voltage threshold setting for the reset time

delay period tPOR of 200ms (See Figure 1)

The ISL88012, ISL88014 and ISL88015 allow users to

customize the minimum voltage sense level on the VMON

input pin. To do this, connect an external resistor divider

network to the VMON pin in order to set the trip point to some

voltage above 600mV according to the following Equation 1

(See Figure 2).

:

VINTRIP = 0.6  ---R----1---R--+--2---R----2----

(EQ. 1)

Power-On Reset (POR)

Applying at least 1V to the VDD pin activates a POR circuit

which asserts reset (i.e., RST goes HIGH while RST goes

LOW). The reset signals remain asserted until the voltage at

VDD and/or VMON rise above the minimum voltage sense

level for time period tPOR. This ensures that the voltages have

stabilized.

These reset signals provide several benefits:

• It prevents the system microprocessor from starting to

operate with insufficient voltage.

• It prevents the processor from operating prior to stabilization

of the oscillator.

• It ensures that the monitored device is held out of operation

until internal registers are properly loaded.

• It allows time for an FPGA to download its configuration prior

to initialization of the circuit.

Adjusting POR Timeout via CPOR Pin

On the ISL88011 and ISL88014, users can adjust the

Power-On Reset timeout delay (tPOR) up to many times the

normal tPOR of 250ms. To do this, connect a capacitor

between CPOR and ground (see Figure 3). For example,

connecting a 30pF capacitor to CPOR will increase tPOR from a

typical 250ms to about 2.5s. NOTE: Care should be taken in

PCB layout and capacitor placement in order to reduce stray

capacitance as much as possible, which lengthens the tPOR

timeout period.

CPOR

ISL88011

ISL88014

R1 VMON

VIN

R2

ISL88012

ISL88014

ISL88015

FIGURE 2. USING VMON TO MONITOR VIN VIA RESISTORS

6

5

4

3

2

1

0

0 10 20 30 40 50 60 70 80

CPOR (pF)

FIGURE 3. ADJUSTING tPOR WITH A CAPACITOR

FN8093 Rev 5.00

December 4, 2015

Page 9 of 15

Share Link: