MAX3057ASA データシートの表示（PDF） - Maxim Integrated
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MAX3057ASA Datasheet PDF : 12 Pages
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MAX3050/MAX3057
±80V Fault-Protected, 2Mbps, Low-Supply
Current CAN Transceivers
Timing Characteristics
(VCC = +5V ±10%, RL = 60Ω, CL = 100pF, TA = TMIN to TMAX. Typical values are at VCC = +5V and TA = +25°C.) (Figures 1, 2, and 3)
PARAMETER
TIMING
Minimum Bit Time
Delay TXD to Bus Active
Delay TXD to Bus Inactive
Delay TXD to Receiver Active
Delay TXD to Receiver Inactive
Differential Output Slew Rate
Bus Dominant to RXD Low
Time to Wake Up: CANH > 9V
Time to Sleep Mode when Bus Is
Recessive
SYMBOL
CONDITIONS
tBIT
tONTXD
tOFFTXD
tONRXD
tOFFRXD
SR
tWAKE
VRS = 0 (2Mbps)
RRS = 24kΩ (500kbps)
RRS = 100kΩ (125kbps)
RRS = 180kΩ (62.5kbps)
VRS = 0
VRS = 0
VRS = 0 (2Mbps)
RRS = 24kΩ (500kbps)
RRS = 100kΩ (125kbps)
RRS = 180kΩ (62.5kbps)
VRS = 0 (2Mbps)
RRS = 24kΩ (500kbps)
RRS = 100kΩ (125kbps)
RRS = 180kΩ (62.5kbps)
RRS = 24kΩ (500kbps)
RRS = 100kΩ (125kbps)
RRS = 180kΩ (62.5kbps)
Standby mode
SHDN = GND, VTXD = VCC (MAX3050)
tSHDN CSHDN = 100nF (MAX3050)
MIN TYP MAX UNITS
0.5
2
µs
8
25
40
ns
75
ns
120
ns
0.4
1.6
µs
5.0
130
ns
0.45
1.6
µs
5.0
14
7
V/µs
1.6
10
µs
10
µs
10
47
ms
Note 1: As defined by ISO, bus value is one of two complementary logical values: dominant or recessive. The dominant value
represents the logical 1 and the recessive represents the logical 0. During the simultaneous transmission of the dominant
and recessive bits, the resulting bus value is dominant. For MAX3050 and MAX3057 values, see the truth table in the
Transmitter and Receiver sections under Detailed Description.
Note 2: The ESD structures do not short out CANH and CANL under an ESD event while -7V < CANH, CANL < +12V.
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