PCA9530 データシートの表示（PDF） - Philips Electronics
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PCA9530 Datasheet PDF : 16 Pages
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Philips Semiconductors
2-bit I2C LED dimmer
Preliminary data
PCA9530
POWER-ON RESET
When power is applied to VDD, an internal Power On Reset holds
the PCA9530 in a reset state until VDD has reached VPOR. At this
point, the reset condition is released and the PCA9530 registers are
initialized to their default states, all the outputs in the off state.
EXTERNAL RESET
A reset can be accomplished by holding the RESET pin low for a
minimum of tW. The PCA9530 registers and I2C state machine will
be held in their default state until the RESET input is once again
high.
This input requires a pull-up resistor to VDD.
CHARACTERISTICS OF THE I2C-BUS
The I2C-bus is for 2-way, 2-line communication between different ICs
or modules. The two lines are a serial data line (SDA) and a serial
clock line (SCL). Both lines must be connected to a positive supply
via a pull-up resistor when connected to the output stages of a device.
Data transfer may be initiated only when the bus is not busy.
Bit transfer
One data bit is transferred during each clock pulse. The data on the
SDA line must remain stable during the HIGH period of the clock
pulse as changes in the data line at this time will be interpreted as
control signals (see Figure 5).
SDA
SCL
data line
stable;
data valid
change
of data
allowed
SW00363
Figure 5. Bit transfer
Start and stop conditions
Both data and clock lines remain HIGH when the bus is not busy. A
HIGH-to-LOW transition of the data line, while the clock is HIGH is
defined as the start condition (S). A LOW-to-HIGH transition of the
data line while the clock is HIGH is defined as the stop condition (P)
(see Figure 6).
System configuration
A device generating a message is a transmitter: a device receiving
is the receiver. The device that controls the message is the master
and the devices which are controlled by the master are the slaves
(see Figure 7).
SDA
SDA
SCL
S
SCL
P
START condition
STOP condition
Figure 6. Definition of start and stop conditions
SW00365
SDA
SCL
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
Figure 7. System configuration
MASTER
TRANSMITTER/
RECEIVER
SLAVE
I2C
MULTIPLEXER
SW00366
2002 Dec 12
5
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