SPT7710 データシートの表示（PDF） - Cadeka Microcircuits LLC.

部品番号

コンポーネント説明

メーカー

SPT7710

8-BIT, 150 MSPS, FLASH A/D CONVERTER

Cadeka Microcircuits LLC. 

Figure 2 – Typical Interface Circuit 2 (PGA and Cerquad packages only)

*See below

+

U1

RT

–

Voltage

Limiter

VCC

+

–U1

VCC

Analog

Input

10 W Force

22

Q1 D1

DGND AGND

VEE

L

–5.2 V

2.2 µF

.01 µF

VEE

VRTF

VIN

LINV

MINV

Typical Voltage Limiter

RS

49.9

D1

D2

–5.2

U1 and U2=

Rail-to-Rail Op Amp

D1=HP, 1N5712

Q1=1N2222A

Q2=1N2907A

R = 1 kW, .1%

VRTS

Preamp Comparator

256

Clock

Buffer

R

192

191

+

U2

10-25 W VR3

–

.01 µF

151

R

+ 10-25 W VR2

128

U2

–

.01 µF

127

R

10-25 W

64

+

U2

VR1

–

.01 µF

63

R

2

VREF

VEE

–2 V

+

22 W

1

U2

–

VRBF

VEE .01 µF

VRBS

Convert

100116

CLK

2

CLK

Analog Input VIN

(Sense)

.01 µF

–2 V

(Analog)

256 to

8-Bit

Encoder

ECL

Latches

And

Buffers

AGND

VEE

AGND

.01 µF

.01 µF

–5.2 V

VEE

Overrange

D8

MSB

D7

D6

D5

D4

D3

D2

D1

LSB

D0

DRINV

DREAD

50 W

–2 V

–2 V (Digital)

50 W

.01 µF

double-sided PC board with a ground plane on the compo-

nent side separated into digital and analog sections will

give the best performance. The converter is bonded-out to

place the digital pins on the left side of the package and

the analog pins on the right side. Additionally, an RF bead

connection through a single point from the analog to digi-

tal ground planes will reduce ground noise pickup.

The circuit in figure 2 (PGA and cerquad packages only) is

intended to show the most elaborate method of achieving

the least error by correcting for integral nonlinearity, input

induced distortion, and power supply/ground noise. This is

achieved by the use of external reference ladder tap con-

nections, an input buffer, and supply decoupling. The func-

tion of each pin and external connections to other compo-

nents is as follows:

VEE, AGND, DGND

VEE is the supply pin with AGND as ground for the device.

The power supply pins should be bypassed as close to the

device as possible with at least a .01 µF ceramic capaci-

tor. A 1 µF tantalum should also be used for low frequency

suppression. DGND is the ground for the ECL outputs and

is to be referenced to the output pulldown voltage and

appropriately bypassed as shown in figure 1.

VIN (ANALOG INPUT)

There are two analog input pins that are tied to the same

point internally. Either one may be used as an analog input

sense and the other for input force. This is convenient for

testing the source signal to see if there is sufficient drive

capability. The pins can also be tied together and driven by

SPT7710

6

8/17/01

Share Link: