EVAL-AD5755-1SDZ データシートの表示（PDF） - Analog Devices

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EVAL-AD5755-1SDZ

Quad Channel, 16-Bit, Serial Input, 4 mA to 20 mA Output DAC, Dynamic Power Control, HART Connectivity

Analog Devices 

Data Sheet

REVISION HISTORY

6/2017—Rev. F to Rev. G

Changes to Figure 4........................................................................8

Changes to Figure 5........................................................................9

Changes to Readback Operation Section....................................32

Deleted Table 27 and Table 28; Renumbered Sequentially........32

Changes to Asynchronous Clear Section....................................34

9/2014—Rev. E to Rev. F

Changes to Table 3..........................................................................7

Changes to Pin 21 and Pin 29 Descriptions................................12

Changes to Pin 51 and Pin 59 Descriptions................................13

Changes to Figure 45......................................................................21

Changes to Software Register and Status Register Descriptions.25

Changes to Software Register Section, Table 21,and Table 22...31

Changed Bit 11 of the Status Register; Table 30 and Table 31...34

Changes to Packet Error Checking Section................................36

Changes to HART Section...........................................................37

6/2014—Rev. D to Rev. E

Change to Thermal Hysteresis Parameter and Power

Dissipation Parameter, Table 1 ......................................................6

Changes to Table 3..........................................................................7

Changes to Figure 4........................................................................8

AddedFigure 5; Renumbered Sequentially, Changes to Figure 6....9

Change to Figure 30......................................................................17

Changes to Figure 34, Figure 35, Figure 36, and Figure 37 .......19

Changes to Figure 45 and Figure 47............................................21

Change to Voltage Reference Thermal Hysteresis Definition...22

Changes to Table 6........................................................................25

Changes to Table 11 and Table 13................................................28

Changes to Software Register Section, Table 21, and Table 22.......31

Changes to Readback Operation Section, Added Table 27 and

Table 28; Renumbered Sequentially............................................32

Changes to Status Register Section, Table 30, and Table 31 ......34

Changes to Status Readback During a Write Section................35

Changes to Packet Error Checking Section................................36

Changes to Table 35......................................................................38

Change to External PMOS Mode Section and Figure 63 ..........40

11/2012—Rev. C to Rev. D

Changed Thermal Impedance from 20°C/W to 28°C/W..........10

Changes to Pin 6 Description......................................................11

Changes to DUT_AD1, DUT_AD0 Description, Table 8.........27

Changes to Changes to Packet ErrorChecking Section and

Internal Reference Section...........................................................35

Changes to Figure 57....................................................................37

Changes to Figure 63....................................................................41

Changes to Figure 66....................................................................43

Updated Outline Dimensions......................................................44

AD5757

5/2012—Rev. B to Rev. C

Changes to Companion Products Section....................................1

Changes to Table 5........................................................................13

Added Industrial HART Capable Analog Output Application

Section and Figure 66, Renumbered Sequentially......................43

Updated Outline Dimensions......................................................44

11/2011—Rev. A to Rev. B

Change to Test Conditions/Commentsof Accuracy (External

RSET) Parameter, Table 1..................................................................5

Changes to Figure 4........................................................................8

Changes to Figure 5........................................................................9

Change to Pin 8 Description, Table 5..........................................11

Change to Figure 13......................................................................14

Change to Figure 20......................................................................16

Changes to Figure 48 and Power-On State of the AD5757

Section ...........................................................................................23

Change to Table 16.......................................................................29

Changes to Readback Operation Section, Readback Example

Section, and Table 25....................................................................32

Change to Figure 54......................................................................35

Change to Figure 58 Caption.......................................................38

Changes to Figure 59, Figure 60, and Figure 61 Captions.........39

Changes to Transient Voltage Protection Section and

Figure 63........................................................................................41

Changes to Galvanically Isolated Interface Section...................42

5/2011—Rev. 0 to Rev. A

Changes Features Section...............................................................1

Changes to Figure 2........................................................................3

Changed AVDD Min Parameter from 10.8 V to 9 V......................5

Changes to Pin 22, Pin31, Pin 49 Descriptions..........................11

Changes to Pin 58 Descriptions...................................................12

Changes to Figure 8, Figure 9, and Figure 10.............................13

Added Figure 23, Renumbered Sequentially..............................15

Added Figure 29............................................................................16

Added External PMOS Mode Section and Figure 62 ................38

4/2011—Revision 0: Initial Version

Rev. G | Page 3 of 45

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