MCC141563T データシートの表示（PDF） - Motorola => Freescale

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MCC141563T

32K x 8 Bit Static Random Access Memory

Motorola => Freescale 

WRITE CYCLE 1 (W Controlled, See Notes 1 and 2)

6706BR–6

6706BR–7

6706BR–8

Parameter

Symbol Min Max Min Max Min Max Unit Notes

Write Cycle Time

Address Setup Time

Address Valid to End of Write

Write Pulse Width

tAVAV

6

—

7

—

8

— ns

3

tAVWL

0

—

0

—

0

— ns

tAVWH

6

—

7

—

8

— ns

tWLWH, 6

—

7

—

8

— ns

tWLEH

Data Valid to End of Write

Data Hold Time

Write Low to Data High–Z

Write High to Output

Active

tDVWH

3

— 3.5 — 3.5 — ns

tWHDX

0

—

0

—

0

— ns

tWLQZ

—

3.5

—

3.5

—

3.5

ns 4, 5, 6

tWHQX

3

—

3

—

3

— ns 4, 5, 6

Write Recovery Time

tWHAX

0

—

0

—

0

— ns

NOTES:

1. A write occurs during the overlap of E low and W low.

2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus

contention conditions during read and write cycles.

3. All write cycle timings are referenced from the last valid address to the first transitioning address.

4. Transition is measured 200 mV from steady–state voltage with load of Figure 1b.

5. Parameter is sampled and not 100% tested.

6. At any given voltage and temperature, tWLQZ max is < tWHQX min both for a given device and from device to device.

A (ADDRESS)

E (CHIP ENABLE)

W (WRITE ENABLE)

D (DATA IN)

Q (DATA OUT)

WRITE CYCLE 1

tAVAV

tAVWL

HIGH–Z

tWLQZ

tAVWH

tWLEH

tWLWH

tDVWH

DATA VALID

HIGH–Z

tWHAX

tWHDX

tWHQX

MOTOROLA FAST SRAM

MCM6706BR

5

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