SPT7725AIJ データシートの表示（PDF） - Signal Processing Technologies

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SPT7725AIJ

8-BIT, 300 MSPS FLASH A/D CONVERTER

Signal Processing Technologies 

GENERAL DESCRIPTION

The SPT7725 is a fast monolithic 8-bit parallel flash A/D

converter. The nominal conversion rate is 300 MSPS and the

analog bandwidth is in excess of 200 MHz. A major advance

over previous flash converters is the inclusion of 256 input

preamplifiers between the reference ladder and input com-

parators. (See block diagram.) This not only reduces clock

transient kickback to the input and reference ladder due to a

low AC beta but also reduces the effect of the dynamic state

of the input signal on the latching characteristics of the input

comparators. The preamplifiers act as buffers and stabilize

the input capacitance so that it remains constant for varying

input voltages and frequencies and therefore makes the part

easier to drive than previous flash converters. The SPT7725

incorporates a proprietary decoding scheme that reduces

metastable errors (sparkle codes or flyers) to a maximum of

1 LSB.

The SPT7725 has true differential analog and digital data

paths from the preamplifiers to the output buffers (Current

Mode Logic) for reducing potential missing codes while

rejecting common mode noise.

Signature errors are also reduced by careful layout of the

analog circuitry. Every comparator also has a clock buffer to

reduce differential delays and to improve signal-to-noise

ratio. The output drive capability of the device can provide full

ECL swings into 50 Ω loads.

TYPICAL INTERFACE CIRCUIT

The typical interface circuit is shown in figure 1. The SPT7725

is relatively easy to apply depending on the accuracy needed

in the intended application. Wire-wrap may be employed

with careful point-to-point ground connections if desired, but

to achieve the best operation, a double sided PC board with

a ground plane on the component side separated into digital

and analog sections will give the best performance. The

converter is bonded-out to place the digital pins on the left

side of the package and the analog pins on the right side.

Additionally, an RF bead connection through a single point

from the analog to digital ground planes will reduce ground

noise pickup.

The circuit in figure 2 (PGA and cerquad packages only) is

intended to show the most elaborate method of achieving the

least error by correcting for integral nonlinearity, input in-

duced distortion, and power supply/ground noise. This is

achieved by the use of external reference ladder tap connec-

tions, an input buffer and supply decoupling. The function of

each pin and external connections to other components is as

follows:

Figure 1 - SPT7725 Typical Interface Circuit 1

Optional

+

Buffer

-

Analog Input

Can Be Either Force Or Sense

VRTF

VR2

.01 µF

VREF

-2 V

Analog Input

Can Be Either

Force Or Sense

+ 10-25 Ω

-

OP07 .01 µF

VRBF

VIN

Convert 100116

CLK

CLK

.01 µF

-2 V

(Analog)

L

VIN

AGND

VEE

.01 µF -5.2 V

Preamp Comparator

256

Clock

Buffer

255

MSB D7

152

151

128

256 To

8-Bit

Encoder

127

D6

D5

64

D4

63

D3

2

D2

D1

1

LSB D0

2

LINV

MINV

MSB D7

D6

D5

D4

ECL

Latches

And

Buffers

D3

D2

D1

LSB D0

50 Ω

AGND

.01 µF

VEE

-5.2 V

DGND

.01 µF

-2 V (Digital)

50 Ω

SPT

5

SPT7725

12/30/98

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