SPT7725BIQ データシートの表示（PDF） - Signal Processing Technologies
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SPT7725BIQ Datasheet PDF : 12 Pages
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Figure 2 - SPT7725 Typical Interface Circuit 2 (PGA and Cerquad Packages Only)
Optional
+
Buffer
-
R
DGND AGND
VEE
Analog
Input
10-25 Ω
Force
+
U1
VRTF VIN
-
VRTS
L
-5.2 V
.01 µF
.01 µF
Preamp Comparator
256
Clock
Buffer
192
U1-5: OP07 or
equivalent, low
noise, low offset
amplifier
R = 1 kΩ, .1%
+ 10-25 Ω VR3
U2
-
.01 µF
R
+ 10-25 Ω VR2
U3
-
.01 µF
R
191
151
128
256 to
8-Bit
Encoder
127
LINV
MINV
Overrange
D8
MSB
D7
D6
D5
ECL
Latches
D4
And
Buffers
D3
10-25 Ω
+
U4
VR1
64
-
.01 µF
63
R
2
VREF
-2 V
+
U5
10-25
Ω
VRBF
-
VRBS
.01 µF
CLK
Convert 100116
1
2
CLK
Analog Input
(Sense)
VIN
.01 µF
-2 V
(Analog)
AGND
VEE
AGND
.01 µF
.01 µF
-5.2 V
VEE
D2
D1
LSB
D0
DRINV
DREAD
50 Ω
-2 V
-2 V (Digital)
50 Ω
.01 µF
VEE, AGND, DGND
VEE is the supply pin with AGND as ground for the device.
The power supply pins should be bypassed as close to the
device as possible with at least a .01 µF ceramic capacitor.
A 1 µF tantalum should also be used for low frequency
suppression. DGND is the ground for the ECL outputs and
is to be referenced to the output pulldown voltage and
appropriately bypassed as shown in figure 1.
VIN (ANALOG INPUT)
There are two analog input pins that are tied to the same
point internally. Either one may be used as an analog input
sense and the other for input force. This is convenient for
testing the source signal to see if there is sufficient drive
capability. The pins can also be tied together and driven by
the same source. The SPT7725 is superior to similar de-
vices due to a preamplifier stage before the comparators.
This makes the device easier to drive because it has
constant capacitance and induces less slew rate distortion.
An optional input buffer may be used.
CLK, CLK (CLOCK INPUTS)
The clock inputs are designed to be driven differentially with
ECL levels. The clock may be driven single-ended since
CLK is internally biased to -1.3 V. (See clock input circuit.)
CLK may be left open but a .01 µF bypass capacitor from
CLK to AGND is recommended. NOTE: System perfor-
mance may be degraded due to increased clock noise or
jitter.
MINV, LINV (OUTPUT LOGIC CONTROL)
These are ECL-compatible digital controls for changing the
output code from straight binary to two's complement, etc.
For more information, see table I. Both MINV and LINV are
in the logic low (0) state when they are left open. The high
state can be obtained by tying to AGND through a diode or
3.9 kΩ resistor.
SPT
6
SPT7725
12/30/98
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