AS7C4098A データシートの表示（PDF） - Alliance Semiconductor

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AS7C4098A

5.0 V 256 K × 16 CMOS SRAM

Alliance Semiconductor 

Write waveform 3 9

Address

CE

LB, UB

WE

DataIN

DataOUT

tAS

High Z

®

tWC

tCW

tAW

tBW

tWP

tDW

tWZ

Data undefined

tAH

tWR

Data valid

tDH

High Z

AS7C4098A

AC test conditions

- Output load: see Figure B.

- Input pulse level: GND to VCC - 0.5V. See Figure A.

- Input rise and fall times: 2 ns. See Figure A.

- Input and output timing reference levels: 1.5V.

+5.0V

VCC - 0.5V 90%

90%

10%

10%

GND

2 ns

Figure A: Input pulse

DOUT

255Ω

480Ω

C10

GND

Figure B:5.0V Output load

Thevenin equivalent:

168Ω

DOUT

+1.728V

Notes

1 During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification.

2 For test conditions, see AC Test Conditions, Figures A and B.

3 tCLZ and tCHZ are specified with CL = 5pF as in Figure B. Transition is measured ±500mV from steady-state voltage.

4 This parameter is guaranteed, but not tested.

5 WE is High for read cycle.

6 CE and OE are Low for read cycle.

7 Address valid prior to or coincident with CE transition Low.

8 All read cycle timings are referenced from the last valid address to the first transitioning address.

9 All write cycle timings are referenced from the last valid address to the first transitioning address.

10 C = 30 pF, except on High Z and Low Z parameters, where C = 5 pF.

2/21/06, v 1.2

Alliance Semiconductor

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