LTC6991HS6 データシートの表示（PDF） - Analog Devices

部品番号

コンポーネント説明

メーカー

LTC6991HS6

TimerBlox: Resettable, Low Frequency Oscillator

Analog Devices 

LTC6991

TYPICAL PERFORMANCE CHARACTERISTICS

V+ = 3.3V, RSET = 200k, TA = 25°C unless otherwise noted.

Output Resistance

vs Supply Current

50

45

40

35

OUTPUT SOURCING CURRENT

30

25

20

15 OUTPUT SINKING CURRENT

10

5

0

2

3

4

5

6

SUPPLY VOLTAGE (V)

6991 G22

Typical Start-Up with POL = 1

V+

1V/DIV

OUT

1V/DIV

500µs

1µs (tMASTER) WIDE

INITIAL PULSE

V+ = 2.5V

DIVCODE = 15

RSET = 50k

250µs/DIV

6991 G19

PIN FUNCTIONS (DCB/S6)

V+ (Pin 1/Pin 5): Supply Voltage (2.25V to 5.5V). This

supply should be kept free from noise and ripple. It should

be bypassed directly to the GND pin with a 0.1µF capacitor.

and 50ppm/°C or better temperature coefficient. For lower

accuracy applications an inexpensive 1% thick film resis-

tor may be used.

DIV (Pin 2/Pin 4): Programmable Divider and Polarity

Input. A V+ referenced A/D converter monitors the DIV

pin voltage (VDIV) to determine a 4-bit result (DIVCODE).

VDIV may be generated by a resistor divider between V+

and GND. Use 1% resistors to ensure an accurate result.

The DIV pin and resistors should be shielded from the

OUT pin or any other traces that have fast edges. Limit

the capacitance on the DIV pin to less than 100pF so that

VDIV settles quickly. The MSB of DIVCODE (POL) deter-

mines the polarity of the RST and OUT pins. If POL = 0,

RST is active-high, and forces OUT low. If POL = 1, RST

is active-low and forces OUT high.

SET (Pin 3/Pin 3): Frequency-Setting Input. The voltage

on the SET pin (VSET) is regulated to 1V above GND. The

amount of current sourced from the SET pin (ISET) pro-

grams the master oscillator frequency. The ISET current

range is 1.25µA to 20µA. The output oscillation will stop

if ISET drops below approximately 500nA. A resistor con-

nected between SET and GND is the most accurate way to

set the frequency. For best performance, use a precision

metal or thin film resistor of 0.5% or better tolerance

Limit the capacitance on the SET pin to less than 10pF

to minimize jitter and ensure stability. Capacitance less

than 100pF maintains the stability of the feedback circuit

regulating the VSET voltage.

V+

RST

OUT

LTC6991

GND

V+

SET

RSET

DIV

6991 PF

V+

C1

0.1µF R1

R2

RST (Pin 4/Pin 1): Output Reset. The behavior of the RST

pin is dependent on the polarity bit (POL). The POL bit is

configured via the DIVCODE setting. When POL = 0, set-

ting RST high forces OUT low and setting RST low allows

the output to oscillate. When POL = 1, RST is active low.

In that case, setting RST low forces OUT high and setting

RST high allows the output to oscillate.

For more information www.linear.com/LTC6991

6991fc

7

Share Link: