HEC4040BT,112 データシートの表示（PDF） - NXP Semiconductors.
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HEC4040BT,112 Datasheet PDF : 14 Pages
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NXP Semiconductors
HEF4040B
12-stage binary ripple counter
Table 6. Dynamic characteristics …continued
VSS = 0 V; Tamb = 25 C; unless otherwise specified; for test circuit see Figure 6.
Symbol Parameter
Conditions
VDD
Extrapolation formula[1] Min Typ Max Unit
tt
transition time
see Figure 5
5 V [3] 10 ns + (1.00 ns/pF)CL -
60 120 ns
10 V
9 ns + (0.42 ns/pF)CL -
30 60 ns
15 V
6 ns + (0.28 ns/pF)CL -
20 40 ns
tW
pulse width
CP input HIGH;
minimum width;
see Figure 5
5V
10 V
15 V
50 25 -
ns
30 15 -
ns
20 10 -
ns
MR input HIGH;
minimum width;
see Figure 5
5V
10 V
15 V
40 20 -
ns
30 15 -
ns
20 10 -
ns
trec
recovery time
MR input;
5V
see Figure 5
10 V
40 20 -
ns
30 15 -
ns
15 V
20 10 -
ns
fmax
maximum
frequency
CP input;
see Figure 5
5V
10 V
10 20 -
15 30 -
MHz
MHz
15 V
25 50 -
MHz
[1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).
[2] For loads other than 50 pF at the nth output, use the slope given.
[3] tt is the same as tTHL and tTLH.
Table 7. Dynamic power dissipation PD
PD can be calculated from the formulas shown. VSS = 0 V; tr = tf 20 ns; Tamb = 25 C.
Symbol Parameter
VDD
Typical formula for PD (W)
where:
PD
dynamic power 5 V
PD = 400 fi + (fo CL) VDD2
fi = input frequency in MHz,
dissipation
10 V
PD = 2000 fi + (fo CL) VDD2
fo = output frequency in MHz,
15 V
PD = 5200 fi + (fo CL) VDD2
CL = output load capacitance in pF,
VDD = supply voltage in V,
(fo CL) = sum of the outputs.
HEF4040B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 17 November 2011
© NXP B.V. 2011. All rights reserved.
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