HM5225165B-75 データシートの表示（PDF） - Elpida Memory, Inc

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HM5225165B-75

256M LVTTL interface SDRAM 133 MHz/100 MHz 4-Mword × 16-bit × 4-bank/8-Mword × 8-bit × 4-bank/16-Mword × 4-bit × 4-bank PC/133, PC/100 SDRAM

Elpida Memory, Inc 

HM5225165B/HM5225805B/HM5225405B-75/A6/B6

• Byte control by DQM : DQM (HM5225805B/HM5225405B)

: DQMU/DQML (HM5225165B)

• Refresh cycles: 8192 refresh cycles/64 ms

• 2 variations of refresh

 Auto refresh

 Self refresh

Ordering Information

Type No.

Frequency

CAS latency

HM5225165BTT-75*1

133 MHz

3

HM5225165BTT-A6

100 MHz

2/3

HM5225165BTT-B6*2

100 MHz

3

HM5225165BLTT-75*1

133 MHz

3

HM5225165BLTT-A6

100 MHz

2/3

HM5225165BLTT-B6*2 100 MHz

3

HM5225805BTT-75*1

133 MHz

3

HM5225805BTT-A6

100 MHz

2/3

HM5225805BTT-B6*2

100 MHz

3

HM5225805BLTT-75*1

133 MHz

3

HM5225805BLTT-A6

100 MHz

2/3

HM5225805BLTT-B6*2 100 MHz

3

HM5225405BTT-75*1

133 MHz

3

HM5225405BTT-A6

100 MHz

2/3

HM5225405BTT-B6*2

100 MHz

3

HM5225405BLTT-75*1

133 MHz

3

HM5225405BLTT-A6

100 MHz

2/3

HM5225405BLTT-B6*2 100 MHz

3

Notes: 1. 100 MHz operation at CAS latency = 2.

2. 66 MHz operation at CAS latency = 2.

Package

400-mil 54-pin plastic TSOP II (TTP-54D)

Data Sheet E0082H10

2

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