HM5225165B-75 データシートの表示（PDF） - Elpida Memory, Inc

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HM5225165B-75

256M LVTTL interface SDRAM 133 MHz/100 MHz 4-Mword × 16-bit × 4-bank/8-Mword × 8-bit × 4-bank/16-Mword × 4-bit × 4-bank PC/133, PC/100 SDRAM

Elpida Memory, Inc 

HM5225165B/HM5225805B/HM5225405B-75/A6/B6

Block Diagram (HM5225165B)

Column address

counter

A0 to A8

A0 to A12, BA0, BA1

A0 to A12, BA0, BA1

Column address

buffer

Row address

buffer

Refresh

counter

Row decoder

Memory array

Bank 0

8192 row

X 512 column

X 16 bit

Row decoder

Memory array

Bank 1

8192 row

X 512 column

X 16 bit

Row decoder

Memory array

Bank 2

8192 row

X 512 column

X 16 bit

Row decoder

Memory array

Bank 3

8192 row

X 512 column

X 16 bit

Input

buffer

Output

buffer

DQ0 to DQ15

Control logic &

timing generator

Data Sheet E0082H10

6

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